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G  N Z { k  r w {  N  N    /   / E  G o v     m ŀ ẁ ׀  ܀ U   3 ) > T _ f b  t    >    Ɓ ́  ߁    y a & F. 6 > I  P g  l z     ɂ ΂ 1Ff f Lf Rf x t fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff=u %t=u % ut;D$d$A%=Ut 1 !+4=HQS Z_{ gty~ 000ûѻ000 *4>JVbintel_runtime_resumeintel_runtime_suspendvlv_wait_for_gt_wellsi915_initintel_detect_pchintel_virt_detect_pchw5b%5`5`r%% % %r''@'@r)))))))*`*`B*. . ". 2. B. . BF@" &j-`VfR b Z j " * +.  "   *   +   .   "   *   +   "   *   +   . &  &   &   .   & 0@1@2@3@W@U  ` ```"&+.* - """"  !&@+@*@2@;@=@:@ Z P PP P          <     >     0   *  a#  `        !   B  !B   B   !B    B       !   !     !       !        @0               i965_irq_handler`@`intel_get_hpd_pinsdisplay_pipe_crc_irq_handleri915_irq_handleri8xx_irq_handlersnb_gt_irq_handler @cpt_irq_handler@ibx_irq_handlergen6_rps_irq_handler @ gen8_irq_handler i915_get_crtc_scanoutposi915_get_vblank_timestampivybridge_parity_worki915_reset_and_wakeup@guc_log_levelenable_guc_submissionedp_vswingnuclear_pageflipverbose_state_checksmmio_debuguse_mmio_flipenable_cmd_parserdisable_vtd_wadisable_displayinvert_brightnessload_detect_testprefault_disablefastbootenable_ipsdisable_power_wellpreliminary_hw_supportenable_psrenable_execlistsenable_ppgttenable_hangcheckresetvbt_sdvo_panel_typelvds_use_ssclvds_channel_modeenable_fbcenable_rc6semaphorespanel_ignore_lidmodesetgt_max_freq_mhz_storeerror_state_writepowerintel_csr_ucode_initfinish_csr_loadA0B0C0D0E0F0G0H0I0A0A1A2B0B1B2igigtigTigEig6ig'icherryview_enable_rpsvalleyview_enable_rpsintel_print_rc6_infogen6_enable_rpssandybridge_pcode_writesandybridge_pcode_readintel_init_pmi915_ironlake_get_mem_freqintel_print_wm_latencysnb_wm_latency_quirk 6 f  J   C D   >ލH x, \5 : j&V/ 5e M}s ̄ f jmƐ ae n  R 1a  K {5 L|+[  Fv0 :d W s Aq^Q n<l υ ܂  ς֎ ʌintel_get_cxsr_latencyi830_get_fifo_sizei845_get_fifo_size_? i845_update_wmintel_calculate_wmi9xx_get_fifo_size?@_?@?  i9xx_update_wmi965_update_wmg4x_update_wmg4x_check_srwm? @@?@ @@?@pineview_update_wmvlv_update_wmvlv_pipe_set_fifo_sizegen6_check_mch_setupilk_validate_wm_levelskl_wm_flush_pipeironlake_enable_drpssanitize_rc6_optioncherryview_init_gt_powersavecherryview_setup_pctxvalleyview_init_gt_powersavevalleyview_setup_pctx5-o*&_ &hb5k*k \ironlake_set_drpsQQRvlv_wm_get_hw_statevlv_get_fifo_sizeintel_set_memory_cxsr_ZUUK<>2'chv_phy_control_initvlv_cmnlane_wachv_dpio_cmn_power_well_disablechv_dpio_cmn_power_well_enableskl_set_power_wellskl_disable_dc6skl_enable_dc6gen9_enable_dc5hsw_set_power_wellsanitize_disable_power_well_optionintel_power_well_disableintel_power_well_enablechv_phy_powergate_laneschv_phy_powergate_chbxt_disable_dc9bxt_enable_dc9`PгЦPp`P`Pphzpf\RH>4*  tmcOtmZ@&zpq  /23**\**Z7*ZG*08W*08i*0Xy*U*@**P7****++5(+6+@SK+q]+0Iq+G+P>+`=+;+`+:+P+,9,`4&, 2:,psH,(W,'n,0,$,,P!,p ,,,,k- %-<-M-p_-m-~--@- 7-7- 8-8. 9.92. :E.:Z. ;k.;{. <.<. =.=. >.>. ?/?i915_displayport_test_active_write//%/,///2/7/dev, REC->ring, REC->to, REC->vm"dev=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ctx, REC->vm"dev=%u, vm=%p", REC->dev, REC->vm"new_freq=%u", REC->freq"plane=%d, obj=%p", REC->plane, REC->obj"plane=%d, obj=%p", REC->plane, REC->obj"dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%u, seqno=%u, blocking=%s", REC->dev, REC->ring, REC->seqno, REC->blocking ? "yes (NB)" : "no""dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%x, invalidate=%04x, flush=%04x", REC->dev, REC->ring, REC->invalidate, REC->flush"dev=%u, ring=%u, seqno=%u, flags=%x", REC->dev, REC->ring, REC->seqno, REC->flags"dev=%u, sync-from=%u, sync-to=%u, seqno=%u", REC->dev, REC->sync_from, REC->sync_to, REC->seqno"dev=%d, vm=%p", REC->dev, REC->vm"dev=%d", REC->dev"dev=%d, size=%d, align=%d %s", REC->dev, REC->size, REC->align, REC->flags & (1<<0) ? ", mappable" : """obj=%p", REC->obj"obj=%p, %s index=%u %s", REC->obj, REC->gtt ? "GTT" : "CPU", REC->index, REC->write ? ", writable" : """obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, read=%02x=>%02x, write=%02x=>%02x", REC->obj, REC->read_domains >> 16, REC->read_domains & 0xffff, REC->write_domain >> 16, REC->write_domain & 0xffff"vm=%p, pde=%d, updating %u:%u %s", REC->vm, REC->pde, REC->last, REC->first, __get_str(cur_ptes)"vm=%p, pml4e=%d (0x%llx-0x%llx)", REC->vm, REC->px, REC->start, REC->end"vm=%p, pdpe=%d (0x%llx-0x%llx)", REC->vm, REC->px, REC->start, REC->end"vm=%p, pde=%d (0x%llx-0x%llx)", REC->vm, REC->px, REC->start, REC->end"vm=%p (%s), 0x%llx-0x%llx", REC->vm, __get_str(name), REC->start, REC->end"obj=%p, offset=%016llx size=%x vm=%p", REC->obj, REC->offset, REC->size, REC->vm"obj=%p, offset=%016llx size=%x%s vm=%p", REC->obj, REC->offset, REC->size, REC->flags & (1<<0) ? ", mappable" : "", REC->vm"dev=%d, target=%lu, flags=%x", REC->dev, REC->target, REC->flags"obj=%p, size=%u", REC->obj, REC->size"pipe %c, frame=%u, scanline=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline"pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->max"pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->maxintel_lr_context_deferred_allocpopulate_lr_contextintel_init_workaround_bblrc_setup_wa_ctx_objgen8_init_common_ringintel_execlists_submission 80;0 80;0emit_mocs_control_tableemit_mocs_l3cc_tableinit_status_pageinit_ring_commonintel_ring_workarounds_emitintel_init_pipe_control@ABCAPP@ؗؗxhsw_unclaimed_reg_detect 0 0 00 0 0 00 xp J&J.Jintel_guc_ucode_initguc_fw_fetchintel_guc_ucode_loadguc_ucode_xferguc_ucode_xfer_dmaJJJJguc_client_allocselect_doorbell_cachelineassign_doorbellpq $,i yxaax x xxxxxxyyyxAxx@ xN x""3"xx HH @Z`w@ @Z`w` Z`w @Z`w a `" 1!  `@ `` ` ` ` @` ``!` !1$@~~~~~~~~0$  y1luu ia yxy0x@1x2x3xxxxxxx!xx x xxx$x@#x`/x x@ x( x""##x`@*x`y{1  yZw .@Zw`.@1!  .`...@1 Ly`yzix xxx QxxxxxxxPxx xRx0x@1x2x3xyyyyyyyy x x x x xIxJxKxyyy y@y`aayxyy@yyy yxxxy xyyy y xx@@@@ @@@@@ @$@(@,@0@4@8@<@@@D@H@L@P@T@X@\@`@d@h@l@p@t@x@|@C x"" h&x'x(x)x*xx $xOxMx@+x,x-x.x/xx#x`!x{????,@zix xxx Qxxxxx xxPxx xRx0x@1x2x3xyyyyyyyy x x x x xIxJxKxyyy y@y`aayxyy@yyy yxxxy xyyy y xx@@@@ @@@@@ @$@(@,@0@4@8@<@@@D@H@L@P@T@X@\@`@d@h@l@p@t@x@|@C x""Ux hx$xAOxMx@+x,x-x.x/xx#x!x&x'x(x)x*x{????0 i915_audio_component_sync_audio_rateDkD(`J(}o}( fX"X($w-Jw((E(I[J(Phsw_audio_codec_disablehsw_audio_codec_enableWbpbxii&! "CD audio_config_hdmi_pixel_clockilk_audio_codec_disableilk_audio_codec_enableg4x_audio_codec_disableg4x_audio_codec_enableintel_audio_codec_enableintel_atomic_setup_scalers intel_plane_atomic_checkintel_plane_atomic_set_propertyintel_plane_atomic_get_propertyNLENOVO97027RGintel_no_opregion_vbt_callbackinit_vbt_defaultsvalidate_vbtparse_general_featuresparse_general_definitionsparse_lfp_panel_dataparse_lfp_backlightparse_sdvo_panel_dataparse_sdvo_device_mappingparse_device_mappingparse_driver_featuresparse_edpparse_psrparse_mipiparse_ddi_porttranslate_iboostH8((qhx˙P˙˙˙˙000`@( ( 0!intel_modeset_setup_hw_stateintel_modeset_readout_hw_stateintel_sanitize_encoderintel_sanitize_crtcintel_disable_shared_dpllintel_dump_pipe_configintel_dump_crtc_timingsi915_redisable_vga_power_onPintel_modeset_initintel_atomic_commitintel_connector_check_statecheck_encoder_statecheck_crtc_stateintel_pipe_config_comparecheck_shared_dpll_stateintel_modeset_pipe_configconnected_sink_compute_bppironlake_fdi_compute_configironlake_check_fdi_lanesintel_modeset_checkscherryview_set_cdclk@ivb_manual_fdi_link_traingen6_fdi_link_trainironlake_fdi_link_train    intel_hpll_vco0 =UaQa(A0 =UaQ>I0 =UaQa2Kl6A0 =UaQ>I(0 =UaQ>Ia  i9xx_set_pipeconfintel_enable_pipeintel_disable_pipei9xx_pfit_disablei9xx_get_refclk>I;f? Ng5p Ng5P@  H2)>Ib+Hp =[  N\*Fxb N\*FxP@  a0W @`a0W @`!a0W @`!a0W5O~  *na0W5O  8na0W5O~  pna0W5Ov  pna0W5O  Pn 8kg5h * N8g5h pUg5h P ag5h  i9xx_get_initial_plane_configi9xx_crtc_clock_getintel_prepare_shared_dpllcpt_set_fdi_bc_bifurcationintel_enable_shared_dpllironlake_crtc_compute_clockironlake_get_refclkironlake_get_initial_plane_configskylake_pfit_enablelpt_program_iclkipskylake_get_initial_plane_config0-p]90&0$$intel_crtc_initintel_update_pipe_configintel_crtc_atomic_checkintel_crtc_page_flipskl_do_mmio_flipC8 RG16XR24XB24AR24AB24XR30XB30YUYVYVYUUYVYVYUYC8 RG16XR24XB24XR30XB30C8 RG16XR15XR24AR24i9xx_update_cursorintel_check_cursor_planeintel_update_czclkintel_update_cdclkintel_update_max_cdclk\\intel_setup_outputsintel_alloc_initial_plane_obj=<intel_framebuffer_initintel_user_framebuffer_create_handleintel_prepare_plane_fbintel_crtc_restore_modeintel_plane_atomic_calc_changesskl_update_scaler_planeskl_update_scalerintel_release_load_detect_pipeintel_get_load_detect_pipehsw_disable_pc8hsw_enable_pc8ironlake_init_pch_refclkZ!\&!`=j !L skl_set_cdclkbroxton_init_cdclkintel_display_port_aux_power_domainport_to_aux_power_domainport_to_power_domainskl_update_scaler_crtcintel_get_shared_dpllskl_plane_ctl_rotationskl_plane_ctl_tilingskl_plane_ctl_formatintel_fb_stride_alignmentintel_pin_and_fence_fb_objintel_tile_heightd M@ @ @ (,0,8,@,H,P,X,`,h,p,x,,,,, ,i8xx_fbc_disablei8xx_fbc_enableg4x_fbc_disableg4x_fbc_enableilk_fbc_enableilk_fbc_disablegen7_fbc_enableintel_fbc_cancel_work__intel_fbc_updateintel_fbc_alloc_cfbset_no_fbc_reasonintel_no_fbc_reason_strEEEEEintel_hpd_irq_storm_reenable_worki915_hotplug_work_funcintel_hpd_irq_eventintel_hpd_irq_handlerintel_hpd_irq_storm_detect___&_0_4_9_00 0@0@/00 .0, 0`+ 0 *` 0ീ( 0@? 0x<`@0 : @008@0x6 0@4` 0@2@ 0@`1 000`., h@+@ )`(`>(<9@7 64h`3న@2@1`000intel_overlay_attrsintel_overlay_put_imageintel_overlay_continueintel_psr_enableintel_psr_match_conditionsvlv_sideband_rw՚XB24XR24YUYVYVYUUYVYVYUYXR24YUYVYVYUUYVYVYUYRG16AB24AR24XB24XR24XB30AB30YUYVYVYUUYVYVYUYintel_check_sprite_planeskl_update_planeintel_dsm_detectintel_dsm_pci_probes~ONT,intel_dsmintel_dsm_platform_mux_infocelewece|eeeeeeecececeeeeefintel_opregion_setupswsci_setupswsciasle_workasle_set_als_illumasle_set_backlightasle_set_pfitasle_set_pwm_freqasle_set_supported_rotation_anglesasle_set_button_arrayasle_set_convertibleasle_set_dockingasle_isct_stateintel_didl_outputsintel_fbdev_restore_mode`Pintel_fb_initial_configintelfb_createintel_fbdev_init_biosch7017_dump_regsch7017_mode_setch7017_initch7xxx_dump_regsch7xxx_readbch7xxx_writebch7xxx_init-i4i{ IntelD510MO K{ IntelD525MW0 @ p intel_lvds_initintel_lvds_set_propertyintel_lvds_detect X{Apple Inc.MacBookPro6,2 u{Apple Inc.MacBookPro8,2 {Apple Inc.MacBookPro9,1 {TOSHIBATECRA A11intel_lvds_compute_configintel_backlight_device_registerintel_backlight_device_update_statusintel_panel_actually_set_backlightintel_panel_get_backlighti9xx_enable_backlightget_backlight_max_vbtget_backlight_min_vbti965_enable_backlightvlv_enable_backlightpch_enable_backlightlpt_disable_backlightlpt_enable_backlightbxt_enable_backlightintel_panel_setup_backlightintel_panel_enable_backlightintel_panel_disable_backlight intel_sdvo_init  intel_sdvo_write_cmd:Vn  (ހLp $ H l     <  !0'd (M)d* +{, } z  < h ghij΁klUV$W<XTYiZz^_`[т\]ab9cQdiefM NOу{ P Q R( SL Tl mnop6qMt udvw xy؄2Kh ʅ,G`yintel_sdvo_debug_writeintel_sdvo_read_byteintel_sdvo_get_capabilitiesƆ҆چintel_sdvo_read_responseintel_sdvo_output_setupintel_sdvo_dvi_init     320x200@@A320x240@@A400x300@&,-LM640x350@B^_~640x400@J640x480@~X704x480@0` 704x576@0r @A`a720x350@?I0^_~720x400@R0720x480@b0720x540@m0<=720x576@xt0@A`a768x576@R{@`@A`a800x600@ !`XYxy832x624@@Apq920x766@C1024x768@C@` !1280x1024@T@` !intel_sdvo_get_tv_modesintel_sdvo_get_lvds_modesintel_sdvo_get_ddc_modesintel_sdvo_connector_matches_edidintel_sdvo_detectintel_sdvo_tv_init "(.4:@FMT\dlt}intel_sdvo_create_enhance_propertyintel_sdvo_create_enhance_property_tvintel_sdvo_create_enhance_property_lvdsintel_sdvo_analog_initintel_sdvo_lvds_initintel_sdvo_get_configintel_enable_sdvointel_sdvo_write_infoframeintel_sdvo_compute_configP 0N N $ @D|YH" @k@Q\,h,t,,,$ @D|YH" @k 6\,h,t,,,$ @D|YH" @k@Q/00(0, $ @D|YH" @k@A@0L0X0p0,P @L_I"  lq\0000,P @L_I   lqC0001,$@JzY ,,, P@[_ 00?,%@E`P,,q ,/@EPP,, , 9@EPXkO   ,D@E`Xk  , L `K intel_tv_initOW X_hrPz8NTSC 480i@X Pintel_tv_detectintel_tv_detect_type2-EYSMn(Eintel_tv_compute_config q <2-3-@ 2-3jd z=0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(10@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(1q  2-LFZ"2-L"V  q <2-3-@ 2-3jd z= v <2-3-@ 2-3jd z=v2-E?S2-EyOintel_vgt_deballoonc d d d (d c xd `d c c d He c c e c c e e c `e c d d c c c d xe c c d e d 8d Hd (e @dD@AdBd Cd@Dd&Ed@4Fd!c BGd@PHd^Id@iJd @sKd@Ld@Md@NdOd ͌Qd@ތSd@Td(@Udc Vd@c Wd!*Xd!8YdJZd[[d l\d @ |]d @ ^d( _d @ `d@ ad Ѝbd cd dd ed fd ;gd,@ Lhd, cid@@!vjd kd ld!md ˎnd@ od@ pd qd &rd 4sd Itd Zud ti915_getparami915_dump_device_infointel_alloc_mchbar_resourceintel_device_info_runtime_init  $@\x <Xt8Tp4Pl0Lh,Hd (D`|$@\x  < X t       8 T p       4 P l       0 L h       , H d       (D`|$@\x <Xt8Tpd\  :   HLPTX\x|$$$$$$$$$$$$$@.D.H.L.P.T.X.\.`.d.h.l.p.t.x.|................................./// ///// /$/(/,/0/4/8/ (>,>. P>X>> >'>>>{ ? $?'(?P?X?{? ?'????{P@X@`@h@p@CCCCCD D D(D]]]]]^^^ ^^^^^``DaHaPaTaXa\a`aaaaaaaaaaaabbbbb b b b b b b b b b b b b ooooooooop p p lp pp tp xp pp`udu@yDy $@DH LPTX\ ęș̙@D $(,048<@DHLPTX\`dhlptx|Ğ ȞWОԞm؞ܞX 7 pğȟc 8<@DLMPD|Ȭ ̬   $(,048<@DHLPTX\@DHLP                        $ ( ķ ̷ Է ܷ    @D  @ZLPT:X\dhpwxx |`dhlptx|Ŀȿ̿пԿؿܿ $   D H L Z:w@DHLPTX\`dhlptx|$(`Zpt:x|w$@ZPT:\dhpwtx| $(,048<@DHLPTX\`dhlptx|  $ ( , 0 8<@   4@ T` t    |Z:w@DHLPXx Z:w      0 @ H P h p x     8<     hl   LP   04 |   `d   DH   (, tx  `Zpt:x|wx  LP  @D          $  ,  4  <  D L  T  \  d l  t  |                     $ ,4<DLT\ d l t |                    $ , 4<DLT\d l t |                  $ , 4 < D L T        Z04:8<DHPwTX\                    @"ZP"T":X"\"d"h"p"wx"x " ### #$#,# ###### l$p$t$x$|$$ %% %$%(%0% %%%%%% p&t&x&|&&& ,'4' '' (( 0)8) )) ***** * * * * * + @1D1H1L1P1T1X1\1`1d1h1l1p1t1x1|11111111111111111111111U1 1U1 2U 2 2U2 (2U,2 82U<2 H2L2 X2U\2 h2Ul2 x2U|2 2U2 2U2 2U2 2U2 2U2 2U2 2U2 3U3 (38 ,3 83<3 H3L3 X3+\3 h3l3 x3U|3 3U3 3 3 3w3 33 33 33 3$3 3|3 4 4 4y4 (4,4 84<4 H4L4 X4\4 h4el4 x4|4 4U4 4 4 44 44 44 44 4L 4 44 5L 5 5"5 (58,5 85 <5 55GT register access while GT waking disabled failed to load firmware %s (%d) timeout waiting for GFX clock force-on (%08x) drivers/gpu/drm/i915/i915_drv.cRuntime resume failed, disabling it (%d) GEM idle failed, resume might fail Resume prepare failed: %d, continuing anyway failed to re-initialize GPU, declaring wedged! <6>[drm] This hardware requires preliminary hardware support. See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support <6>[drm] Simulated gpu hang, resetting stop_rings <6>[drm] Reset not implemented, but ignoring error for simulated gpu hangs <5>drm/i915: Resetting chip after gpu hang !(IS_GEN6(dev) || IS_IVYBRIDGE(dev))!IS_HASWELL(dev) && !IS_BROADWELL(dev)IS_HSW_ULT(dev) || IS_BDW_ULT(dev)!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)waiting for GT wells to go %s (%08x) (I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != masktimeout waiting for GT wells to go %s !(dev_priv->rps.enabled && intel_enable_rc6(dev))device lock contention, deffering suspend Runtime suspend failed, disabling it (%d) DRM not initialized, aborting suspend. state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZEhotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x Command parser error, iir 0x%08x drivers/gpu/drm/i915/i915_irq.cInterrupt register 0x%x is not zero: 0x%08x enabled_irq_mask & ~interrupt_maskstatus_mask & PIPE_A_PSR_STATUS_VLVstatus_mask & PIPE_B_PSR_STATUS_VLVpipe %c: enable_mask=0x%x, status_mask=0x%x I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_eventsCommand parser error, gt_iir 0x%08x Command parser error, pm_iir 0x%08x PCH audio power change on port %c PCH audio power change on port %d PCH transcoder audio interrupt PCH transcoder CRC done interrupt PCH transcoder CRC error interrupt The master control interrupt lied (GT0)! The master control interrupt lied (GT1)! The master control interrupt lied (GT3)! The master control interrupt lied (PM)! The master control interrupt lied (DE MISC)! The master control interrupt lied (DE PORT)! Fault errors on pipe %c : 0x%08xThe master control interrupt lied (DE PIPE)! The master control interrupt lied (SDE)! trying to get scanoutpos for disabled pipe %c No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx !dev_priv->l3_parity.which_sliceslice >= NUM_L3_SLICES(dev_priv->dev)Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d. dev_priv->l3_parity.which_slicepm_iir & ~dev_priv->pm_rps_events<3>i915: render error detected, EIR: 0x%08x <3>i915: INSTDONE_%d: 0x%08x <3>i915: memory refresh error: <3>i915: pipe %c stat: 0x%08x Hangcheck timer elapsed... %s idle <6>[drm] Fake missed irq on %s drivers/gpu/drm/i915/i915_sysfs.cUser requested overclocking to %d RC6 residency sysfs setup failed RC6p residency sysfs setup failed Media RC6 residency sysfs setup failed l3 parity slice 1 setup failed error_state sysfs setup failed No CSR support available for this platform Unknown stepping info, firmware loading failed Firmware has wrong CSS header length %u bytes Firmware has wrong package header length %u bytes Firmware not supported for %c stepping Firmware has wrong dmc header length %u bytes Firmware has wrong mmio count %u Firmware has wrong mmio address 0x%x CSR firmware too big (%u) bytes Memory allocation failed for dmc payload drivers/gpu/drm/i915/intel_csr.cCSR program storage start is NULL drivers/gpu/drm/i915/intel_pm.cUnsupported pixel depth for rotationEnabling RC6 states: RC6 %s RC6p %s RC6pp %s Unknown FSB/MEM found, disable CxSR FIFO entries required for mode: %ld Pipe %c FIFO split %d / %d / %d Wrong MCH_SSKPD value: 0x%08x This can cause underruns. Primary WM%d too large %u (max %u) Sprite WM%d too large %u (max %u) Cursor WM%d too large %u (max %u) gpu busy, RCS change rejected !mutex_is_locked(&dev_priv->rps.hw_lock)%s WM%d latency %u (%u.%u usec) warning: pcode (write) mailbox access failed timeout waiting for pcode write (%d) to finish warning: pcode (read) mailbox access failed timeout waiting for pcode read (%d) to finish GT fifo had a previous error %x Failed to set the min frequency Overclocking supported. Max: %dMHz, Overclock max: %dMHz Couldn't check for BIOS workaround You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV) Couldn't fix incorrect rc6 voltage (pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0current GPU freq: %d MHz (%u) setting GPU freq to %d MHz (%u) pctx_addr != dev_priv->mm.stolen_base + dev_priv->vlv_pctx->stolen->startdev_priv->rps.max_freq < dev_priv->rps.min_freqdev_priv->rps.idle_freq > dev_priv->rps.max_freqdev_priv->rps.efficient_freq < dev_priv->rps.min_freqdev_priv->rps.efficient_freq > dev_priv->rps.max_freqtimed out waiting for Punit DDR DVFS request Punit not acking DDR DVFS request, assuming DDR DVFS is disabled Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d Setting FIFO watermarks - A: %d self-refresh entries: %d, wm: %d self-refresh watermark: display plane %d cursor %d Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d FIFO watermarks - A: %d, B: %d Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d Setting FIFO watermarks - %c: plane=%d, cursor=%d, sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d fmax: %d, fmin: %d, fstart: %d stuck trying to change perf mode Adjusting RC6 mask to %d (requested %d, valid %d) !mutex_is_locked(&dev->struct_mutex)BIOS didn't set up PCBR, fixing up RP1(Guar) GPU freq: %d MHz (%u) not enough stolen space for PCTX, disabling RP1(Guar Freq) GPU freq: %d MHz (%u) unknown memory frequency 0x%02x WM latency values increased to avoid potential underruns Failed to read display plane latency. Disable CxSR <6>[drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR unexpected fall-through in intel_init_pm SR watermark: display plane %d, cursor %d display watermark is too large(%d/%ld), disabling cursor watermark is too large(%d/%ld), disabling Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d <6>[drm] WARN_ON(!wm_changed) cstate->base.active != intel_crtc->active<6>[drm] RC6 disabled, disabling runtime PM support Getting nosync-ref while suspended. drivers/gpu/drm/i915/intel_runtime_pm.c!power_domains->domain_use_count[domain]toggling display PHY side reset DC9 already programmed to be disabled. Platform doesn't support DC9. DC9 already programmed to be enabled. DC5 still not disabled to enable DC9. Disabling display power well support state != PUNIT_PWRGT_PWR_ON(power_well_id) && state != PUNIT_PWRGT_PWR_GATE(power_well_id)state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x) Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x) timeout setting power well state %08x (%08x) power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BCpower_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && power_well->data != PUNIT_POWER_WELL_DPIO_CMN_DDisabled DPIO PHY%d (PHY_CONTROL=0x%08x) power_well->data != PUNIT_POWER_WELL_DISP2Ddrivers/gpu/drm/i915/intel_drv.hPower gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x) Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x) Display PHY %d is not power up Enabled DPIO PHY%d (PHY_CONTROL=0x%08x) Invalid for power well status to be enabled, unless done by the BIOS, when request is to disable! DC6 already programmed to be disabled. Not Disabling PW1, dmc will handle Platform doesn't support DC6. DC6 already programmed to be enabled. Platform doesn't support DC5. PG2 not disabled to enable DC5. DC5 already programmed to be enabled. DC5 cannot be enabled, if platform is runtime-suspended. PG1 distributing status timeout PG2 distributing status timeout Requesting to disable the power well drivers/gpu/drm/i915/i915_debugfs.cdpcd read (%zu bytes at %u) failed (%zd) FB tracking busy bits: 0x%08x FB tracking flip bits: 0x%08x 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x crtc_mask: 0x%08x, active: %d, on: %s %hu %hu %hu %hu %hu %hu %hu %hu VBT: DRRS_type: FIXME: Unrecognized ValueToggling workaround to %i returns %i expected <%lu bytes into pipe crc control too many words, allowed <= %d tokenize failed, a command is %d words Trying to capture CRC while pipe is off collecting CRCs for pipe %c, %s Masking interrupts on rings 0x%08llx Manually setting uncore sharing to %llu 0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s bit6 swizzle for X-tiling = %s bit6 swizzle for Y-tiling = %s Enabled by kernel parameter: %s Manually setting min freq to %llu Manually setting max freq to %llu Manually setting wedged to %lluFrequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d GuC last action command: 0x%x GuC last action error code: %d %-24s: %10llu, last seqno 0x%08x %9d Priority %d, GuC ctx index: %u, PD offset 0x%x Doorbell id %d, offset: 0x%x, cookie 0x%x WQ size %d, offset: 0x%x, tail %d Master Interrupt Control: %08x Display Engine port interrupt mask: %08x Display Engine port interrupt identity: %08x Display Engine port interrupt enable: %08x Display Engine misc interrupt mask: %08x Display Engine misc interrupt identity: %08x Display Engine misc interrupt enable: %08x North Display Interrupt enable: %08x North Display Interrupt identity: %08x North Display Interrupt mask: %08x South Display Interrupt enable: %08x South Display Interrupt identity: %08x South Display Interrupt mask: %08x Graphics Interrupt enable: %08x Graphics Interrupt identity: %08x Graphics Interrupt mask: %08x Graphics Interrupt mask (%s): %08x Available Subslice Total: %u Available Subslice Per Slice: %u Available EU Per Subslice: %u Has Subslice Power Gating: %s Enabled Subslice Per Slice: %u Enabled EU Per Subslice: %u n >= obj->base.size >> PAGE_SHIFTdrivers/gpu/drm/i915/i915_drv.hBusy frontbuffer bits: 0x%03x Logical Ring Contexts are disabled Execlist status: 0x%08X, context: %u Read pointer: 0x%08X, write pointer 0x%08X Status buffer %d: 0x%08X, context: %u %s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound) %pK: %s%s%s%s %8zdKiB %02x %02x [ (%sgtt offset: %08llx, size: %08llx (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj !mutex_is_locked(&(dev)->mode_config.fb_lock)user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj Fence %d, pin count = %d, object = Total %d objects, %llu bytes, %llu GTT size FBC unsupported on this chipset GPU freq (MHz) Effective CPU freq (MHz) Effective Ring freq (MHz) Render RC6 residency since boot: %u Media RC6 residency since boot: %u RC information inaccurate because somebody holds a forcewake reference RC6 "Locked to RPn" residency since boot: %u RC6+ residency since boot: %u RC6++ residency since boot: %u Hangcheck active, fires in %dms ACTHD = 0x%08llx [current 0x%08llx] PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x Lowest (RPN) frequency: %dMHz Nominal (RP1) frequency: %dMHz Max non-overclocked (RP0) frequency: %dMHz Max overclocked frequency: %dMHz efficient (RPe) frequency: %d MHz PUNIT_REG_GPU_FREQ_STS: 0x%08x Current CD clock frequency: %d kHz Max CD clock frequency: %d kHz Max pixel clock frequency: %d kHz No flip due on pipe %c (plane %c) Flip queued on pipe %c (plane %c) Flip pending (waiting for vsync) on pipe %c (plane %c) Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d Flip not associated with any ring Flip queued on frame %d, (was ready on frame %d), now %d Stall check waiting for page flip ioctl, Current scanout address 0x%08x New framebuffer address 0x%08lx %u [%u] objects, %llu [%llu] bytes in gtt %u [%u] active objects, %llu [%llu] bytes %u [%u] inactive objects, %llu [%llu] bytes %u unbound objects, %llu bytes %u purgeable objects, %llu bytes %u pinned mappable objects, %llu bytes %u fault mappable objects, %llu bytes id %d:"%s" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x CRTC %d: pipe: %c, active=%s (size=%dx%d) fb: %d, pos: %dx%d, size: %dx%d encoder %d: type: %s, connectors: connector %d: type: %s, status: %s cursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s underrun reporting: cpu=%s pch=%s connector %d: type %s, status: %s physical dimensions: %dx%dmm Context on %s with no gem object Failed to get pages for context object [0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x CMD: Abnormal blt cmd length! 0x%08X CMD: Abnormal bsd cmd length! 0x%08X CMD: Abnormal rcs cmd length! 0x%08X Failed to get space for pages dest_obj->pages_pin_count == 0drivers/gpu/drm/i915/i915_cmd_parser.cCMD: failed to prepare shadow batch CMD: Failed to set shadow batch to CPU CMD: Failed to vmap shadow batch drivers/gpu/drm/i915/i915_drv.hCMD: Unrecognized command: 0x%08X CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td CMD: Rejected command: 0x%08X CMD: Rejected master-only command: 0x%08X CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d) CMD: Rejected LRM to OACONTROL CMD: Rejected LRM to masked register 0x%08X CMD: Rejected LRI to masked register 0x%08X CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d) CMD: batch set OACONTROL but did not clear it CMD: Got to the end of the buffer w/o a BBE cmd! CMD: cmd_parser_init with unknown ring: %d CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X !mutex_is_locked(&pool->dev->struct_mutex)drivers/gpu/drm/i915/i915_gem_batch_pool.cdrivers/gpu/drm/i915/i915_drv.hdrivers/gpu/drm/i915/i915_gem_context.c!mutex_is_locked(&dev_priv->dev->struct_mutex)Failed to change address space on context switch !dev_priv->ring[RCS].last_contextdctx->legacy_hw_ctx.rcs_state->activedev_priv->ring[RCS].default_context<6>[drm] Only EXECLIST mode is supported in vgpu. Disabling HW Contexts; invalid size %d Failed to create default global context (error %ld) %s context support initialized __i915_vma_unbind_no_wait(vma)drivers/gpu/drm/i915/i915_drv.hinclude/asm-generic/dma-mapping-common.h!mutex_is_locked(&vm->dev->struct_mutex)drivers/gpu/drm/i915/i915_gem_evict.cn >= obj->base.size >> PAGE_SHIFTdrivers/gpu/drm/i915/i915_drv.hentry->flags & __EXEC_OBJECT_NEEDS_MAP && !i915_is_ggtt(vma->vm)drivers/gpu/drm/i915/i915_gem_execbuffer.cInvalid object handle %d at index %d Object %p [handle %d, index %d] appears more than once in object list !mutex_is_locked(&req->ring->dev->struct_mutex)non-0 rel constants mode on non-RCS rel surface constants mode invalid on gen5+ execbuf with unknown constants: %d Unexpected failure to bind target VMA!reloc with multiple write domains: obj %p target %d offset %d read %08x write %08xreloc with read/write non-GPU domains: obj %p target %d offset %d read %08x write %08xRelocation beyond object bounds: obj %p target %d offset %d size %d. Relocation not 4-byte aligned: obj %p target %d offset %d. Impossible case in relocation handling UXA submitting garbage DR4, fixing up execbuf with unknown ring: %d execbuf with non bsd ring but with invalid bsd dispatch flags: %d execbuf with unknown bsd ring: %d execbuf with invalid ring: %d RS is only allowed for Haswell, Gen8 and above Context %u tried to submit while banned Attempting to use self-modifying batch buffer Failed to allocate exec list for %d buffers copy %d exec entries failed %d failed to copy %d exec entries back to user failed to copy %d exec entries back to user (%d) Couldn't read from MCHBAR. Disabling tiling. Failed to allocate memory for bit 17 record dev_priv->fence_regs[obj->fence_reg].pin_count <= 0drivers/gpu/drm/i915/i915_gem_fence.cbogus fence setup with stride: 0x%x, tiling mode: %i object 0x%08llx not 512K or pot-size 0x%08x aligned object 0x%08llx [fenceable? %d] not 1M or pot-size (0x%08x) aligned !ggtt_vma || dev_priv->fence_regs[obj->fence_reg].pin_count > ggtt_vma->pin_count!mutex_is_locked(&req->ring->dev->struct_mutex)drivers/gpu/drm/i915/i915_drv.hdrivers/gpu/drm/i915/i915_gem_gtt.cGGTT view %u not implemented! First entry = %d; Num entries = %d (max=%d) Missing switch case (%lu) in %s i915_is_ggtt(vm) != !!ggtt_view<6>[drm] Memory usable by graphics device = %lluM <6>[drm] VT-d active for gfx access <6>[drm] Disabling PPGTT because VT-d is on disabling PPGTT on pre-B3 step VLV Failed to map the gtt page table readq(>t_entries[i-1]) != gen8_pte_encode(addr, level, true)Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)). Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)) Failed to get pages for GGTT view type %u! Failed to get pages for VMA view type %u (%d)! gtt != vm->pte_encode(addr, level, true, flags)<6>[drm] applying Ironlake quirks for intel_iommu !list_empty(&ppgtt->base.active_list)!list_empty(&ppgtt->base.inactive_list) PDE #%d mismatch: Actual PDE: %x Expected PDE: %x Unexpected fault Addr: 0x%08lx Address space: %s Source ID: %d Type: %d i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)Forced to use aperture for PDEs Allocated pde space (%lldM) at GTT entry: %llx reserving preallocated space: %llx + %zx clearing unused GTT space: [%lx, %lx] dev_priv->gtt.base.bind_vma != ggtt_bind_vmastart_in + length_in > ppgtt->base.totalbitmap_empty(pt->used_ptes, GEN6_PTES)!bitmap_empty(pt->used_ptes, GEN6_PTES)drivers/gpu/drm/i915/i915_gem_gtt.h!bitmap_empty(new_page_tables, I915_PDES)!gen8_pte_count(pd_start, pd_len)!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)The allocation has spanned more than 512GB. It is highly likely this is incorrect.!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)drivers/gpu/drm/i915/i915_gem.cvm == &dev_priv->mm.aliasing_ppgtt->base%s vma for this object not found. !mutex_is_locked(&old->base.dev->struct_mutex)!(old->frontbuffer_bits & frontbuffer_bits)!mutex_is_locked(&new->base.dev->struct_mutex)new->frontbuffer_bits & frontbuffer_bitsdrivers/gpu/drm/i915/i915_gem_gtt.hglobal vma for this object not found. (view=%u) (gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)drivers/gpu/drm/i915/i915_drv.hTimed out waiting for the gpu reset to complete Attempting to obtain a purgeable object !req || !file || req->file_privcontext hanging too fast, banning! gpu hanging too fast, banning! *_ring_flush_all_caches failed: %d! i915_gem_object_needs_bit17_swizzle(obj)!mutex_is_locked(&req->ring->dev->struct_mutex)!i915_gem_obj_ggtt_bound_view(obj, view)Failed to initialize GuC, error %d%s PPGTT enable ring #%d failed %d Context enable ring #%d failed %d Failed to initialize GPU, declaring it wedged Attempting to mmap a purgeable buffer Incomplete copy, wrote %zu of %zucan not change the cache level of pinned objects flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)(flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLEi915_is_ggtt(vm) != !!ggtt_viewvma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNTbo is already pinned in %s with incorrect alignment: offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d, obj->map_and_fenceable=%d Invalid object (view type=%u) alignment requested %u Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu flags & PIN_MAPPABLE && !obj->map_and_fenceable!i915_gem_valid_gtt_space(vma, obj->cache_level)unhandled error in i915_gem_fault: %i drivers/gpu/drm/i915/i915_gem_render_state.c(i) >= PAGE_SIZE / sizeof(u32)<3>Unable to purge GPU memory due lock contention. <6>Purging GPU memory, %lu bytes freed, %lu bytes still pinned. <3>%lu and %lu bytes still available in the bound and unbound GPU page lists. drivers/gpu/drm/i915/i915_gem_stolen.c<6>[drm] DMAR active, disabling use of stolen memory GTT within stolen memory at 0x%llx-0x%llx Stolen memory adjusted to 0x%x-0x%x conflict detected with stolen region: [0x%08x - 0x%08x] (reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *baseMissing switch case (%lu) in %s Stolen reserved area [0x%08lx - 0x%08lx] outside stolen memory [0x%08lx - 0x%08lx] Memory reserved for graphics device: %zuK, usable: %luK creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x failed to allocate stolen space failed to allocate stolen object failed to allocate stolen GTT space drivers/gpu/drm/i915/i915_drv.hcreating stolen object: size=%x drivers/gpu/drm/i915/i915_drv.hdrivers/gpu/drm/i915/i915_gem_userptr.cn >= obj->base.size >> PAGE_SHIFTdrivers/gpu/drm/i915/i915_drv.hdrivers/gpu/drm/i915/i915_gpu_error.c %08x_%08x %8u %02x %02x [ Active process (on ring %s): %s [%d] FAULT_TLB_DATA: 0x%08x 0x%08x SYNC_0: 0x%08x [last synced 0x%08x] SYNC_1: 0x%08x [last synced 0x%08x] SYNC_2: 0x%08x [last synced 0x%08x] --- gtt_offset = 0x%08x %08x %s (w/a) --- gtt_offset = 0x%08x seqno 0x%08x, emitted %ld, tail 0x%08x out of memory, not capturing error state <6>[drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. <6>[drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel <6>[drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. <6>[drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. <6>[drm] GPU crash dump saved to /sys/class/drm/card%d/error drivers/gpu/drm/i915/./i915_trace.hpipe %c, frame=%u, scanline=%u, min=%u, max=%u i915_pipe_update_vblank_evadedpipe %c, frame=%u, scanline=%u obj=%p, offset=%016llx size=%x%s vm=%p obj=%p, offset=%016llx size=%x vm=%p vm=%p, pde=%d (0x%llx-0x%llx) i915_page_directory_entry_allocvm=%p, pdpe=%d (0x%llx-0x%llx) i915_page_directory_pointer_entry_allocvm=%p, pml4e=%d (0x%llx-0x%llx) vm=%p, pde=%d, updating %u:%u %s obj=%p, read=%02x=>%02x, write=%02x=>%02x dev=%u, sync-from=%u, sync-to=%u, seqno=%u dev=%u, ring=%u, seqno=%u, flags=%x dev=%u, ring=%x, invalidate=%04x, flush=%04x dev=%u, ring=%u, seqno=%u, blocking=%s dev=%u, ring=%u, ctx=%p, ctx_vm=%p !mutex_is_locked(&req->ring->dev->struct_mutex)drivers/gpu/drm/i915/i915_drv.hprofile buffer not large enough__index >= (PAGE_SIZE / sizeof(uint32_t))drivers/gpu/drm/i915/intel_lrc.c!mutex_is_locked(&ring->dev->struct_mutex)!mutex_is_locked(&req->ring->dev->struct_mutex)drivers/gpu/drm/i915/i915_drv.hfailed to quiesce %s whilst cleaning up: %d %s :timed out trying to stop ring &target->list == &ring->request_listctx->engine[ring->id].pin_count(I915_READ_MODE(ring) & MODE_IDLE) == 0ctx->legacy_hw_ctx.rcs_state != NULLINTEL_INFO(ring->dev)->gen < 8Alloc LRC backing obj failed. n >= obj->base.size >> PAGE_SHIFTFailed to pin and map ringbuffer %s: %d MOCS failed to program: expect performance issues. non-0 rel constants mode on non-RCS rel surface constants mode invalid on gen5+ execbuf with unknown constants: %d !i915_gem_obj_is_pinned(ctx_obj)!i915_gem_obj_is_pinned(rb_obj)!intel_irqs_enabled(ring->dev->dev_private)More than 2 already-submitted reqs queued Lite Restored request removed from queue Preemption without Lite Restore More than two context complete events? Failed get_pages for context obj WA batch buffer is not initialized for Gen%d scratch page not allocated for %s alloc LRC WA ctx backing obj failed. pin LRC WA ctx backing obj failed: %d Failed to setup context WA page: %d wa_ctx_bb failed sanity checks: size %d is not aligned to %d WA batch buffer initialization failed: %d table->size > GEN9_NUM_MOCS_ENTRIESdrivers/gpu/drm/i915/intel_mocs.cintel_logical_ring_begin failed %d Platform that should have a MOCS table does not. %s : timed out trying to stop ring timed out waiting for the BSD ring to wake up drivers/gpu/drm/i915/intel_ringbuffer.crequest reserved size too small: %d vs %d! &request->list == &ring->request_listfailed to quiesce %s whilst cleaning up: %d Failed to allocate ringbuffer %s: %d %s head not reset to zero ctl %08x head %08x tail %08x start %08x failed to set %s head to zero ctl %08x head %08x tail %08x start %08x (I915_READ_MODE(ring) & MODE_IDLE) == 0%s initialization failed [head=%08x], fudging %s initialization failed ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx] %s: wait for SyncFlush to complete for TLB invalidation timed out Failed to allocate seqno page %s pipe control offset: 0x%08x !IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0Failed to allocate status page Failed to pin and map ringbuffer %s: %d Number of Workarounds emitted: %d wait_mbox == MI_SEMAPHORE_SYNC_INVALIDFailed to allocate semaphore bo. Disabling semaphores Failed to pin semaphore bo. Disabling semaphores Unclaimed register before interrupt drivers/gpu/drm/i915/intel_uncore.cloop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIESUnclaimed register detected %s %s register 0x%x %s: timed out waiting for forcewake ack to clear. %s: timed out waiting for forcewake ack request. GT thread status wait timed out domain_id >= FW_DOMAIN_ID_COUNTUnclaimed register detected, enabling oneshot unclaimed register reporting. Please use i915.mmio_debug=N for more information. Timed out waiting for forcewake timers to finish <6>[drm] No MT forcewake available on Ivybridge, this can result in issues <6>[drm] when using vblank-synced partial screen updates. dev_priv->uncore.fw_domains == 0No GuC firmware known for this platform GuC firmware pending, path %s before requesting firmware: GuC fw fetch status %s fetch GuC fw from %s succeeded, fw %p firmware file size %zu (minimum %zu, maximum %zu) GuC firmware version %d.%d, required %d.%d firmware version %d.%d OK (minimum %d.%d) GuC fw fetch status SUCCESS, obj %p GuC fw fetch status FAIL; err %d, fw %p, obj %p Failed to fetch GuC firmware from %s (error %d) DMA status 0x%x, GuC status 0x%x GuC firmware signature verification failed GuC fw status: fetch %s, load %s GuC fw %s invalid guc_fw_fetch_status %s [%d] drivers/gpu/drm/i915/intel_guc_loader.cdrivers/gpu/drm/i915/i915_guc_submission.cGUC: host2guc action 0x%X failed. ret=%d status=0x%08X response=0x%08X n >= obj->base.size >> PAGE_SHIFTdrivers/gpu/drm/i915/i915_drv.h!i915_gem_obj_is_pinned(ctx_obj)!i915_gem_obj_is_pinned(rb_obj)Cookie mismatch. Expected %d, returned %d selected doorbell cacheline 0x%x, next 0x%x, linesize %u assigned %s priority doorbell id 0x%x new priority %u client %p: ctx_index %u db_id %u FAILED to create priority %u GuC client! Failed to create execbuf guc_client drivers/gpu/drm/i915/intel_audio.cHDMI audio pixel clock setting for %d not found, falling back to defaults Configuring HDMI audio for pixel clock %d (0x%08x) Enable audio codec, %u bytes ELD Using automatic mode for N value on port %c Disable audio codec on pipe %c Disable audio codec on port %c, pipe %c Enable audio codec on port %c, pipe %c, %u bytes ELD failed to add audio component (%d) Enable audio codec on pipe %c, %u bytes ELD ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s] !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)drivers/gpu/drm/i915/intel_atomic.cToo many scaling requests %d > %d Failed to add [PLANE:%d] to drm_state intel_plane->pipe != intel_crtc->pipeAttached scaler id %u.%u to %s:%d drivers/gpu/drm/i915/intel_atomic_plane.cY/Yf tiling required for 90/270! Unsupported pixel format %s for 90/270! Falling back to manually reading VBT from VBIOS ROM for %s BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d BDB_GD too small (%d). Invalid. DRRS supported mode is static DRRS supported mode is seamless DRRS not supported (VBT input) Found panel mode in BIOS VBT tables: Unsupported backlight data entry size %u PWM backlight not present in VBT (type %u) VBT backlight PWM modulation frequency %u Hz, active %s, min brightness %u, level %u Ignore SDVO panel mode from BIOS VBT tables. Found SDVO panel mode in BIOS VBT tables: No general definition block is found, unable to construct sdvo mapping. Unsupported child device size for SDVO mapping. the SDVO device with slave addr %2x is found on %s port SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d Maybe one SDVO port is shared by two SDVO device. there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs. No SDVO device info is found in VBT No general definition block is found, no devices defined. Expected child device config size for VBT version %u not known; assuming %u Child device config size %u is too small. Unexpected child device config size %u (expected %u for VBT version %u) no child dev is parsed from VBT No memory space for child device No eDP BDB found but eDP panel supported. VBT has unknown eDP link rate value %u VBT has unknown eDP lane count value %u VBT has unknown eDP pre-emphasis value %u VBT has unknown eDP voltage swing value %u VBT has unknown PSR lines to wait %u Found MIPI Config block, panel index = %d No MIPI Sequence found, parsing complete Unable to parse MIPI Sequence Block v3+ Sequence start is beyond sequence block size, corrupted sequence block Sequence block detected but no valid configuration Corrupted sequence/size, bailing out Sequence elements going beyond block itself. Sequence block parsing failed MIPI related vbt parsing complete More than one child device for port %c in VBT. Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d Internal DP port %c is TMDS compatible Analog port %c is also DP or TMDS compatible Port %c is not DP/TMDS/CRT compatible Unexpected DDC pin for port B Unexpected DDC pin for port C Unexpected DDC pin for port D Unexpected AUX channel for port A Unexpected AUX channel for port B Unexpected AUX channel for port C Unexpected AUX channel for port D VBT HDMI level shift for port %c: %d Unsupported I_boost value found in VBT (%d), display may not work properly VBT (e)DP boost level for port %c: %d VBT HDMI boost level for port %c: %d Unknown pnv display core clock 0x%04x mismatch in cpu_transcoder (expected %i, found %i) mismatch in has_pch_encoder (expected %i, found %i) mismatch in fdi_lanes (expected %i, found %i) mismatch in fdi_m_n (expected tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i) mismatch in has_dp_encoder (expected %i, found %i) mismatch in lane_count (expected %i, found %i) mismatch in dp_m_n (expected tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i) mismatch in dp_m2_n2 (expected tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i) mismatch in dp_m_n (expected tu %i gmch %i/%i link %i/%i, or tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i) mismatch in base.adjusted_mode.crtc_hdisplay (expected %i, found %i) mismatch in base.adjusted_mode.crtc_htotal (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hblank_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hblank_end (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hsync_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hsync_end (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vdisplay (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vtotal (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vblank_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vblank_end (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vsync_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vsync_end (expected %i, found %i) mismatch in pixel_multiplier (expected %i, found %i) mismatch in has_hdmi_sink (expected %i, found %i) mismatch in limited_color_range (expected %i, found %i) mismatch in has_infoframe (expected %i, found %i) mismatch in has_audio (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_INTERLACE) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PHSYNC) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NHSYNC) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PVSYNC) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NVSYNC) (expected %i, found %i) mismatch in gmch_pfit.control (expected 0x%08x, found 0x%08x) mismatch in gmch_pfit.pgm_ratios (expected %i, found %i) mismatch in gmch_pfit.lvds_border_bits (expected 0x%08x, found 0x%08x) mismatch in pipe_src_w (expected %i, found %i) mismatch in pipe_src_h (expected %i, found %i) mismatch in pch_pfit.enabled (expected %i, found %i) mismatch in pch_pfit.pos (expected 0x%08x, found 0x%08x) mismatch in pch_pfit.size (expected 0x%08x, found 0x%08x) mismatch in scaler_state.scaler_id (expected %i, found %i) mismatch in ips_enabled (expected %i, found %i) mismatch in double_wide (expected %i, found %i) mismatch in ddi_pll_sel (expected 0x%08x, found 0x%08x) mismatch in shared_dpll (expected %i, found %i) mismatch in dpll_hw_state.dpll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.dpll_md (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.fp0 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.fp1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.wrpll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.spll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.ctrl1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.cfgcr1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.cfgcr2 (expected 0x%08x, found 0x%08x) mismatch in pipe_bpp (expected %i, found %i) mismatch in base.adjusted_mode.crtc_clock (expected %i, found %i) mismatch in port_clock (expected %i, found %i) Bad HPLL VCO (HPLLVCO=0x%02x) Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x drivers/gpu/drm/i915/intel_display.cCurrent CD clock rate: %d kHz scaler_user index %u.%u: Staged freeing scaler id %d scaler_users = 0x%x scaler_user index %u.%u: src %ux%u dst %ux%u size is out of scaler range scaler_user index %u.%u: staged scaling request for %ux%u->%ux%u scaler_users = 0x%x Updating scaler for [CRTC:%i] scaler_user index %u.%u using SSC reference clock of %d kHz clock->n == 0 || clock->p == 0clock->n + 2 == 0 || clock->p == 0Unknown DPLL mode %08x in programmed mode I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLEI915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE(tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)crtc->config->scaler_state.scaler_id < 0Requesting pfit without getting a scaler first for crtc_state = %p scaler_id = %d !drm_modeset_is_locked(&dev->mode_config.connection_mutex)FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i Updating scaler for [PLANE:%d] scaler_user index %u.%u [PLANE:%d] scaling with color key not allowed[PLANE:%d] FB:%d unsupported scaling format 0x%x [CRTC:%i] has [PLANE:%i] with fb %i [PLANE:%i] visible %i -> %i, off %i, on %i, ms %i Missing switch case (%lu) in %s Suspending crtc's failed with %i [CRTC:%d]%s config %p for pipe %c fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u crtc timings: %d %d %d %d %d %d %d %d %d, type: 0x%x flags: 0x%x num_scalers: %d, scaler_users: 0x%x, scaler_id: %d gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x pch pfit: pos: 0x%08x, size: 0x%08x, %s ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x ddi_pll_sel: %u; dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, fp0: 0x%x, fp1: 0x%x %s PLANE:%d plane: %u.%u idx: %d disabled, scaler_id = %d %s PLANE:%d plane: %u.%u idx: %d enabled FB:%d, fb = %ux%u format = 0x%x scaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u !pll->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)unknown pipe linked to edp transcoder FDI_RX_IIR before link train 0x%x FDI train 1 fail on vswing %d FDI train 2 fail on vswing %d Something enabled VGA plane, disabling it mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u)) mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u)) <6>[drm] Backlight polarity reversed on %s <6>[drm] applying backlight present quirk <6>[drm] applying inverted panel brightness quirk <6>[drm] applying lvds SSC disable quirk <6>[drm] applying pipe b force quirk <6>[drm] applying pipe a force quirk plane %c assertion failure, should be disabled but not <6>[drm] plane %c assertion failure, should be disabled but not plane %c assertion failure, should be off on pipe %c but is still active <6>[drm] plane %c assertion failure, should be off on pipe %c but is still active plane %d assertion failure, should be off on pipe %c but is still active <6>[drm] plane %d assertion failure, should be off on pipe %c but is still active sprite %c assertion failure, should be off on pipe %c but is still active <6>[drm] sprite %c assertion failure, should be off on pipe %c but is still active FDI TX state assertion failure (expected %s, current %s) <6>[drm] FDI TX state assertion failure (expected %s, current %s) FDI RX state assertion failure (expected %s, current %s) <6>[drm] FDI RX state assertion failure (expected %s, current %s) PCH DP (0x%08x) enabled on transcoder %c, should be disabled <6>[drm] PCH DP (0x%08x) enabled on transcoder %c, should be disabled IBX PCH dp port still using transcoder B <6>[drm] IBX PCH dp port still using transcoder B PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled <6>[drm] PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled IBX PCH hdmi port still using transcoder B <6>[drm] IBX PCH hdmi port still using transcoder B transcoder assertion failed, should be off on pipe %c but is still active <6>[drm] transcoder assertion failed, should be off on pipe %c but is still active WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))) <6>[drm] WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))) PCH refclk assertion failure, should be active but is disabled <6>[drm] PCH refclk assertion failure, should be active but is disabled pipe %c assertion failure (expected %s, current %s) <6>[drm] pipe %c assertion failure (expected %s, current %s) I915_READ(PFIT_CONTROL) & PFIT_ENABLEpanel assertion failure, pipe %c regs locked <6>[drm] panel assertion failure, pipe %c regs locked FDI RX PLL assertion failure (expected %s, current %s) <6>[drm] FDI RX PLL assertion failure (expected %s, current %s) asserting DPLL %s with no DPLL %s assertion failure (expected %s, current %s) <6>[drm] %s assertion failure (expected %s, current %s) !(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))disable %s (active %d, on? %d) for crtc %d enable %s (active %d, on? %d) for crtc %d PLL state assertion failure (expected %s, current %s) <6>[drm] PLL state assertion failure (expected %s, current %s) trying to change cdclk frequency with cdclk not enabled failed to inform pcode about cdclk change cdclk requested %d kHz but got %d kHz Switching back to LCPLL failed PCode CDCLK freq change notify failed (err %d, freq %d) timout waiting for DE PLL unlock timeout waiting for DE PLL lock PCode CDCLK freq set failed, (err %d, freq %d) timed out waiting for port %c ready: got 0x%x, expected 0x%x dev_priv->display.get_display_clock_speed(dev) != dev_priv->cdclk_freqI915_READ(GCI_CONTROL) & PFI_CREDIT_RESENDtimed out waiting for CDclk change WARN_ON(drm_crtc_vblank_get(crtc) == 0) <6>[drm] WARN_ON(drm_crtc_vblank_get(crtc) == 0) 128-bit pixels are not supported for display!pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x drivers/gpu/drm/i915/intel_drv.hUpdating pipe size %ix%i -> %ix%i rejecting invalid cloning configuration pipe_config->shared_dpll != DPLL_ID_PRIVATE[CRTC:%d] crtc restore failed, out of memory!mutex_is_locked(&req->ring->dev->struct_mutex)drivers/gpu/drm/i915/i915_drv.h!mutex_is_locked(&obj->base.dev->struct_mutex)Couldn't get view from plane state!Invalid cursor width/stride, width=%u, stride=%u Cursor dimension %dx%d not supported CHV cursor C not allowed to straddle the left screen edge !mutex_is_locked(&dev->struct_mutex)tiling_mode doesn't match fb modifier Unsupported fb modifier 0x%llx! pitch (%d) must be at least %u byte aligned %s pitch (%u) must be at less than %d pitch (%d) must match tiling stride (%d) attempting to use a userptr for a framebuffer, denied Kicking stuck page flip: queued at %d, now %d failed to inform PCU about cdclk change CRTC:%d using pre-allocated %s CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d) Couldn't find PLL settings for mode! failed to find PLL for pipe %c waitqueue_active(&dev_priv->pending_flip_queue)wait_event_timeout(dev_priv->pending_flip_queue, !intel_crtc_has_pending_flip(crtc), 60*HZ) == 0ggtt vma for display object not found! (view=%u) drm_rect_width(&plane_state->src) == 0Y tiling bo slipped through, driver bug! failed to pin boot fb on pipe %d flip queue: previous flip completed, continuing flip queue: crtc already busy DSI PLL state assertion failure (expected %s, current %s) <6>[drm] DSI PLL state assertion failure (expected %s, current %s) cursor on pipe %c assertion failure (expected %s, current %s) <6>[drm] cursor on pipe %c assertion failure (expected %s, current %s) disabling pfit, current: 0x%08x PCH VGA enabled on transcoder %c, should be disabled <6>[drm] PCH VGA enabled on transcoder %c, should be disabled PCH LVDS enabled on transcoder %c, should be disabled <6>[drm] PCH LVDS enabled on transcoder %c, should be disabled failed to disable transcoder %c Failed to disable PCH transcoder FDI TX PLL assertion failure, should be active but is disabled <6>[drm] FDI TX PLL assertion failure, should be active but is disabled !((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))plane %c assertion failure (expected %s, current %s) <6>[drm] plane %c assertion failure (expected %s, current %s) sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)Timed out waiting for IPS enable sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)Timed out waiting for IPS disable failed to enable transcoder %c mode set failed: pipe %c stuck SBI_SSCDIVINTPHASE_DIVSEL(divsel) & ~SBI_SSCDIVINTPHASE_DIVSEL_MASKiCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x Failed to enable PCH transcoder i915 does not yet support async commit connector enabled without attached crtc <6>[drm] connector enabled without attached crtc connector is active, but attached crtc isn't <6>[drm] connector is active, but attached crtc isn't atomic encoder doesn't match attached encoder <6>[drm] atomic encoder doesn't match attached encoder attached encoder crtc differs from connector crtc <6>[drm] attached encoder crtc differs from connector crtc attached crtc is active, but connector isn't <6>[drm] attached crtc is active, but connector isn't best encoder set without crtc! <6>[drm] best encoder set without crtc! connector's atomic encoder doesn't match legacy encoder <6>[drm] connector's atomic encoder doesn't match legacy encoder connector's crtc doesn't match encoder crtc <6>[drm] connector's crtc doesn't match encoder crtc encoder's enabled state mismatch (expected %i, found %i) <6>[drm] encoder's enabled state mismatch (expected %i, found %i) encoder detached but still enabled on pipe %c. <6>[drm] encoder detached but still enabled on pipe %c. crtc active state doesn't match with hw state (expected %i, found %i) <6>[drm] crtc active state doesn't match with hw state (expected %i, found %i) transitional active state does not match atomic hw state (expected %i, found %i) <6>[drm] transitional active state does not match atomic hw state (expected %i, found %i) [ENCODER:%i] active %i with crtc active %i <6>[drm] [ENCODER:%i] active %i with crtc active %i Encoder connected to wrong pipe %c <6>[drm] Encoder connected to wrong pipe %c <6>[drm] pipe state doesn't match! more active pll users than references: %i vs %i <6>[drm] more active pll users than references: %i vs %i pll in active use but not on in sw tracking <6>[drm] pll in active use but not on in sw tracking pll in on but not on in use in sw tracking <6>[drm] pll in on but not on in use in sw tracking pll on state mismatch (expected %i, found %i) <6>[drm] pll on state mismatch (expected %i, found %i) pll active crtcs mismatch (expected %i, found %i) <6>[drm] pll active crtcs mismatch (expected %i, found %i) pll enabled crtcs mismatch (expected %i, found %i) <6>[drm] pll enabled crtcs mismatch (expected %i, found %i) <6>[drm] pll hw state mismatch FDI mPHY reset assert timeout FDI mPHY reset de-assert timeout has_panel %d has_lvds %d has_ck505 %d <6>[drm] CRTC for pipe %c enabled D_COMP RCOMP still in progress requested cdclk (%d kHz) exceeds max (%d kHz) [CONNECTOR:%d:%s], [ENCODER:%d:%s] Couldn't release load detect pipe. unknown plane in flip command !intel_fb->obj->framebuffer_references--[CONNECTOR:%d:%s] checking for sink bpp constrains clamping display bpp (was %d) to EDID reported max of %d clamping display bpp (was %d) to default limit of 24 checking fdi config on pipe %c, lanes %i invalid fdi lane config on pipe %c: %i lanes only 2 lanes on haswell, required: %i lanes invalid shared fdi lane config on pipe %c: %i lanes only 2 lanes on pipe %c: required %i lanes fdi link B uses too many lanes to enable link C fdi link bw constraint, reducing pipe bpp to %i loop in pipe configuration computation CRTC bw constrained, retrying hw max bpp: %i, pipe bpp: %i, dithering: %i rejecting conflicting digital port configuration no pipe available for load-detect creating tmp fb for load-detection reusing fbdev for load-detection framebuffer failed to allocate framebuffer for load-detection failed to set mode on load-detect pipe [CRTC:%d] hw state readout: %s %s hw state readout: crtc_mask 0x%08x, on %i [ENCODER:%d:%s] hw state readout: %s, pipe %c [CONNECTOR:%d:%s] hw state readout: %s drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)[ENCODER:%d:%s] has active connectors but no active pipe! [ENCODER:%d:%s] manually disabled [CRTC:%d] wrong plane connection detected! [CRTC:%d] hw state adjusted, was %s, now %s drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0%s enabled but not in use, disabling Restoring old state failed with %i __i915_wait_request(mmio_flip->req, mmio_flip->crtc->reset_counter, false, NULL, &mmio_flip->i915->rps.mmioflips)SSC %sabled by BIOS, overriding VBT which says %sabled Unknown platform. Assuming 133 MHz CDCLK swapping pipes & planes for FBC drm_crtc_index(&intel_crtc->base) != intel_crtc->pipepipe %c sprite %c init failed: %d enabled FBC, pitch %d, yoff %d, plane %c FBC enabled but currently disabled in hardwaremode incompatible with compressionmode too large for compressionframebuffer not tiled or fencedframebuffer stride not supportedMissing switch case (%lu) in %s drivers/gpu/drm/i915/intel_fbc.c!mutex_is_locked(&dev_priv->fbc.lock)cancelling pending FBC enable <6>[drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. reserved %llu bytes of contiguous stolen space for FBC, threshold: %d <6>drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this. disabling active FBC for update Failed to allocate FBC work structure unsupported config, disabling FBC drivers/gpu/drm/i915/intel_fifo_underrun.c<6>[drm] uncleared pch fifo underrun on pch transcoder %c <6>[drm] PCH transcoder %c FIFO underrun <6>[drm] uncleared fifo underrun on pipe %c <6>[drm] CPU pipe %c FIFO underrun !mutex_is_locked(&dev->struct_mutex)drivers/gpu/drm/i915/intel_frontbuffer.cReenabling HPD on connector %s running encoder hotplug functions drivers/gpu/drm/i915/intel_hotplug.c<6>[drm] HPD interrupt storm detected on connector %s: switching from hotplug detection to polling Connector %s (pin %i) received hotplug event. !mutex_is_locked(&dev->mode_config.mutex)[CONNECTOR:%d:%s] status updated from %s to %s Received HPD interrupt on pin %d although disabled Received HPD interrupt on PIN %d - cnt: 0 HPD interrupt storm detected on PIN %d Received HPD interrupt on PIN %d - cnt: %d Overlay, status: 0x%08x, interrupt: 0x%08x drivers/gpu/drm/i915/intel_overlay.cfailed to attach phys overlay regs failed to pin overlay register bo failed to move overlay register bo into the GTT <6>[drm] initialized overlay support !mutex_is_locked(&req->ring->dev->struct_mutex)drivers/gpu/drm/i915/i915_drv.h!mutex_is_locked(&dev->struct_mutex)!drm_modeset_is_locked(&dev->mode_config.connection_mutex)buffer used for overlay image can not be tiled IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE)I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLEdrivers/gpu/drm/i915/intel_psr.cTimed out waiting for PSR Idle for re-enable vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)Timed out waiting for PSR Idle State PSR transition took longer than expected PSR not supported on this platform PSR not supported by this panel !drm_modeset_is_locked(&dev->mode_config.connection_mutex)!drm_modeset_is_locked(&crtc->mutex)PSR condition failed: Stereo 3D is Enabled PSR condition failed: Interlaced is Enabled PSR condition failed: Link Standby requested/needed but not supported on this platform !mutex_is_locked(&dev_priv->sb_lock)drivers/gpu/drm/i915/intel_sideband.ctimeout waiting for SBI to become ready timeout waiting for SBI to complete write transaction timeout waiting for SBI to complete read transaction IOSF sideband idle wait (%s) timed out IOSF sideband finish wait (%s) timed out !mutex_is_locked(&dev_priv->rps.hw_lock)DPIO read pipe %c reg 0x%x == 0x%x Unsuitable framebuffer for plane drivers/gpu/drm/i915/intel_sprite.cHorizontal scaling factor out of limits Vertical scaling factor out of limits src->x1 < (int) state->base.src_x || src->y1 < (int) state->base.src_y || src->x2 > (int) state->base.src_x + state->base.src_w || src->y2 > (int) state->base.src_y + state->base.src_hSource dimensions exceed hardware limits plane = %d PS_PLANE_SEL(plane) = 0x%x Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d drm_crtc_vblank_get(&crtc->base)Potential atomic update failure on pipe %c no _DSM method for intel device failed to get supported _DSM functions vga_switcheroo: detected DSM switching method %s handle <6>[drm] ACPI BIOS requests an excessive sleep of %u ms, using %u ms instead SWSCI request already in progress graphic opregion physical addr: 0x%x Public ACPI methods supported SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x) SWSCI GBDA callbacks %08x, SBCB callbacks %08x No request on ASLC interrupt 0x%08x updating opregion backlight %d/255 Button array event is not supported (nothing) Button array event is not supported (rotation lock) Button array event is not supported (volume down) Button array event is not supported (volume up) Button array event is not supported (windows) Button array event is not supported (power) Convertible is not supported (clamshell) Convertible is not supported (slate) Docking is not supported (docked) Docking is not supported (undocked) i >= ARRAY_SIZE(opregion->acpi->did2)drivers/gpu/drm/i915/intel_opregion.cMore than %u outputs detected via ACPI More than %u outputs in connector list unsupported intel_encoder type %d drivers/gpu/drm/i915/intel_fbdev.cconnector %s not enabled, skipping connector %s is disabled by user, skipping connector %s has no encoder or crtc, skipping fallback: cloned configuration looking for cmdline mode on connector %s looking for preferred mode on connector %s %d using first mode listed on connector %s looking for current mode on connector %s connector %s on pipe %c [CRTC:%d]: %dx%d%s fallback: Not all outputs enabled Not using firmware configuration INTEL_INFO(dev)->num_pipes == 0pipe %c not active or no fb, skipping found possible fb from plane %c no active fbs found, not using BIOS config checking plane %c for BIOS fb fb not wide enough for plane %c (%d vs %d) pipe %c area: %dx%d, bpp: %d, size: %d fb not big enough for plane %c (%d vs %d) fb big enough for plane %c (%d >= %d) BIOS fb not suitable for all pipes, not using re-used BIOS config but lost an fb on crtc %d using BIOS fb for initial console BIOS fb too small (%dx%d), we require (%dx%d), releasing it no BIOS fb, allocating a new one failed to allocate framebuffer allocated %dx%d fb: 0x%08llx, bo %p CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT: %02x CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT: %02x CH7017_VERTICAL_ACTIVE_LINE_OUTPUT: %02x CH7017_ACTIVE_INPUT_LINE_OUTPUT: %02x CH7017_LVDS_PLL_VCO_CONTROL: %02x CH7017_LVDS_PLL_FEEDBACK_DIV: %02x Registers before mode setting ch701x not detected, got %d: from %s slave %d. Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. ch7xxx not detected; got 0x%02x from %s slave %d. Detected %s chipset, vendor/device ID 0x%02x/0x%02x Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. ivch detect failed due to address mismatch (%d vs %d) Unable to read register 0x%02x from %s:0x%02x. Unable to write register 0x%02x to %s:%d set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d). Detailed requested mode settings are: clock : %d kHz hdisplay : %d hblank start : %d hblank end : %d hsync start : %d hsync end : %d htotal : %d hskew : %d vdisplay : %d vblank start : %d hblank end : %d vsync start : %d vsync end : %d vtotal : %d is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d) Trying set the dpms of the DVO to %i ns2501 not detected got %d: from %s Slave %d. init ns2501 dvo controller successfully! Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. sil164 not detected got %d: from %s Slave %d. init sil164 dvo controller successfully! Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. tfp410 not detected got VID %X: from %s Slave %d. tfp410 not detected got DID %X: from %s Slave %d. CRT GMBUS EDID read failed, retry using GPIO bit-banging drivers/gpu/drm/i915/intel_crt.cCRT detected via DDC:0x50 [EDID] CRT not detected via DDC:0x50 [EDID reports a digital panel] CRT not detected via DDC:0x50 [no valid EDID found] trigger hotplug detect cycle: adpa=0x%x timed out waiting for FORCE_TRIGGERironlake hotplug adpa=0x%x, result %d valleyview hotplug adpa=0x%x, result %d timed out waiting for FORCE_DETECT to go off<6>[drm] Skipping CRT initialization for %s VBT says port %c is not DVI/HDMI/DP compatible, respect it Timeout waiting for DDI BUF %c idle bit Vswing programming not done for encoder %d Disabled scaling while ouniqetrangenmethod was setUnsupported voltage swing/pre-emphasis level: 0x%x %d encoders on crtc for pipe %c drivers/gpu/drm/i915/intel_ddi.cintel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLLFDI link training done on step %d pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONEInvalid encoder type %d for pipe %c compute_config() on unknown output! lane stagger config different for lane 01 (%08x) and 23 (%08x) timeout during PHY%d power on No pipe for ddi port %c found pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp ddi translation table missing No valid divider found for %dHz failed to find PLL for pipe %c no PLL dividers found for clock %d pipe %c spll->hw_state.spll != crtc_state->dpll_hw_state.spllDisabling mst crtc failed with %i drivers/gpu/drm/i915/intel_dp_mst.cTimed out waiting for ACT sent failed to %s sink power state drivers/gpu/drm/i915/intel_dp.c(I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0invalid max DP link bw val %x, using 1.62Gbps panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x picked pipe %c power sequencer for port %c drivers/gpu/drm/i915/intel_drv.hskipping pipe %c power seqeuncer kick due to port %c being active kicking pipe %c power sequencer for port %c cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d panel power up delay %d, power down delay %d, power cycle delay %d backlight on delay %d, off delay %d PP_STATUS: 0x%08x PP_CONTROL: 0x%08x detaching pipe %c power sequencer from port %c pipe != PIPE_A && pipe != PIPE_Bstealing pipe %c power sequencer from port %c stealing pipe %c power sequencer from active eDP port %c no initial power sequencer for port %c initial power sequencer for port %c: pipe %c VDD left on by BIOS, adjusting state tracking dp port still on, should be off 160MHz cpu eDP clock, might need ilk devA w/a DP training pattern 3 not supported mask %08x value %08x status %08x control %08x Panel status timeout: status %08x control %08x Turn eDP port %c panel power off Need eDP port %c VDD to turn off panel Wait for panel power off time <6>[drm] eDP port %c VDD not forced onpipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp No pipe for dp port 0x%x found Refresh rate should be positive non-zero. DRRS: intel_crtc not initialized Only Seamless DRRS supported. DRRS requested for previously set RR...ignoring eDP encoder disabled. CRTC not Active eDP Refresh Rate set to : %dHz Missing switch case (%lu) in %s Sink CRC couldn't be stopped properly Unreliable Sink CRC counter: Current returned CRC is identical to the previous one Panel is unable to calculate any CRC after 6 vblanks Unsupported voltage swing/pre-emphasis level:0x%x DP link computation with max lane count %i max bw %d pixel clock %iKHz clamping bpp for eDP panel to BIOS-provided %i DP link bw %02x rate select %02x lane count %d clock %d bpp %d DP link bw required %i available %i failed to enable link training too many full retries, give up too many voltage retries, give up failed to update link training 5.4 Gbps link rate without HBR2/TPS3 support failed to start channel equalization Channel EQ done. DP Training successful Timed out waiting for DP idle patterns channel EQ not ok, retraining failed to get ESI - device may have failed Display Port TPS3 support: source %s, sink %s Broken DP branch device, ignoring Could not read test request from sink EDID read had %d NACKs, %d DEFERs Failed to write EDID checksum Could not write test response to sink CP or sink specific irq unhandled IS_VALLEYVIEW(dev) && is_edp(intel_dp) && port != PORT_B && port != PORT_CAdding %s connector on port %c drm_dp_aux_register() for %s failed (%d) sysfs_create_link() for %s failed (%d) <6>[drm] failed to retrieve link info, disabling eDP DRRS supported for Gen7 and above Downclock mode is not found. DRRS not supported seamless DRRS supported for eDP panel. using pipe %c for initial backlight setup !drm_modeset_is_locked(&dev->mode_config.connection_mutex)Test request in short pulse not handled %s: channel EQ not ok, retraining ignoring long hpd on eDP port %c MST device may have disappeared %d vs %d panel power control backlight %s eDP port %c panel power wasn't enabled eDP port %c VDD already requested on <6>[drm] eDP port %c VDD already requested on eDP powered off while attempting aux channel communication. dp_aux_ch not started status 0x%08x send_bytes > 20 || recv_size > 20dp aux hw did not signal timeout (has irq: %i)! dp_aux_ch not done status 0x%08x dp_aux_ch receive error status 0x%08x dp_aux_ch timeout status 0x%08x Turn eDP port %c panel power on eDP port %c panel power already on initializing pipe %c power sequencer for port %c Unsupported Mipi device to reg baseTimeout waiting for HS/LP DATA FIFO !full Timeout waiting for HS/LP CTRL FIFO !full Timeout waiting for read data. Same special packet %02x twice in a row. Video mode command 0x%08x send failed. Unsupported MIPI element, skipping sequence execution Burst mode freq is less than computed Values crossing maximum limits, restricting to max values Dual link: DSI_DUAL_LINK_FRONT_BACK Dual link: DSI_DUAL_LINK_PIXEL_ALT Generic Read not yet implemented or used DCS Read not yet implemented or used Timeout waiting for PLL lock deassertion DSI PLL already enabled. Disabling it. drivers/gpu/drm/i915/intel_dsi_pll.cCant get a suitable ratio from DSI PLL ratios Configure DSI PLL failed, abort PLL enable Timed out waiting for DSI PLL to lock Invalid DSI pll ratio(%u) programmed bpp match assertion failure (expected %d, current %d) HDMI port enabled, expecting disabled drivers/gpu/drm/i915/intel_hdmi.c!drm_modeset_is_locked(&dev->mode_config.connection_mutex)Writing DIP with CTL reg disabled Enabling HDMI audio on pipe %c drivers/gpu/drm/i915/intel_drv.hMissing switch case (%lu) in %s DIP already enabled on port %c video DIP still enabled on port %c video DIP already enabled on port %c picking bpc to 12 for HDMI output picking bpc to 8 for HDMI output forcing pipe bpc to %i for HDMI unsupported HDMI clock, rejecting mode %sabling bit-banging on %s. force bit now %d !intel_gmbus_is_valid_pin(dev_priv, pin)drivers/gpu/drm/i915/intel_i2c.cGMBUS [%s] timed out waiting for idle GMBUS [%s] timed out after NAK GMBUS [%s] NAK for addr: %04x %c(%d) GMBUS [%s] NAK on first message, retry <6>[drm] GMBUS [%s] timed out, falling back to bit banging on pin %d <6>[drm] Skipping LVDS initialization for %s <6>[drm] Forcing lvds to dual link mode on %s <6>[drm] Skipping forced modeset for %s LVDS is not present in VBT, but enabled anyway Panel power timings uninitialized, setting defaults using preferred mode from EDID: detected %s-link lvds configuration lid notifier registration failed No LVDS modes found, disabling. timed out waiting for panel to power off forcing display bpp (was %d) to LVDS (%d) timed out waiting for panel to power on Apple Mac Mini (Core 2 series)drivers/gpu/drm/i915/intel_panel.cpipe != PIPE_A && pipe != PIPE_Bbacklight frequency not specified in VBT backlight frequency setting from VBT currently not supported on this platform backlight frequency conversion failed backlight frequency %u Hz from VBT clamping VBT min backlight %d/255 to %d/255 cpu backlight was enabled, disabling pch backlight already enabled updating intel_backlight, brightness=%d/%d Failed to register backlight: %ld Connector %s backlight sysfs interface registered no backlight present per VBT, but present per quirk failed to setup backlight for connector %s Connector %s backlight initialized, %s, brightness %u/%u Skipping backlight disable on vga switch cpu backlight already enabled drivers/gpu/drm/i915/intel_sdvo.cinitialising analog device %d connector_is_digital? %d, monitor_is_digital? %d h_overscan: max %d, default %d, current %d v_overscan: max %d, default %d, current %d hpos: max %d, default %d, current %d vpos: max %d, default %d, current %d saturation: max %d, default %d, current %d contrast: max %d, default %d, current %d hue: max %d, default %d, current %d sharpness: max %d, default %d, current %d brightness: max %d, default %d, current %d flicker_filter: max %d, default %d, current %d flicker_filter_adaptive: max %d, default %d, current %d flicker_filter_2d: max %d, default %d, current %d tv_chroma_filter: max %d, default %d, current %d tv_luma_filter: max %d, default %d, current %d SDVO capabilities: vendor_id: %d device_id: %d device_rev_id: %d sdvo_version_major: %d sdvo_version_minor: %d sdvo_inputs_mask: %d smooth_scaling: %d sharp_scaling: %d up_scaling: %d down_scaling: %d stall_support: %d output_flags: %d %s: Unknown SDVO output type (0x%02x%02x) SDVO output failed to setup on %s %s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c SDVO pixel multiplier mismatch, port: %i, encoder: %i First %s output reported failure to sync SDVO TV clock out of range: %i writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i <6>[drm] Setting output timings on %s failed <6>[drm] Setting input timings on %s failed unknown pixel multiplier specified SDVO_CMD_GET_ATTACHED_DISPLAYSSDVO_CMD_GET_INTERRUPT_EVENT_SOURCESDVO_CMD_GET_INPUT_TIMINGS_PART1SDVO_CMD_GET_INPUT_TIMINGS_PART2SDVO_CMD_SET_INPUT_TIMINGS_PART1SDVO_CMD_SET_INPUT_TIMINGS_PART2SDVO_CMD_SET_OUTPUT_TIMINGS_PART1SDVO_CMD_SET_OUTPUT_TIMINGS_PART2SDVO_CMD_GET_OUTPUT_TIMINGS_PART1SDVO_CMD_GET_OUTPUT_TIMINGS_PART2SDVO_CMD_CREATE_PREFERRED_INPUT_TIMINGSDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTSSDVO_CMD_GET_SUPPORTED_TV_FORMATSSDVO_CMD_GET_SUPPORTED_POWER_STATESSDVO_CMD_SET_ENCODER_POWER_STATESDVO_CMD_SET_DISPLAY_POWER_STATESDVO_CMD_SET_CONTROL_BUS_SWITCHSDVO_CMD_GET_SDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SUPPORTED_ENHANCEMENTSSDVO_CMD_GET_MAX_FLICKER_FILTERSDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_FLICKER_FILTER_ADAPTIVESDVO_CMD_SET_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_MAX_FLICKER_FILTER_2DSDVO_CMD_GET_FLICKER_FILTER_2DSDVO_CMD_SET_FLICKER_FILTER_2DSDVO_CMD_GET_MAX_TV_CHROMA_FILTERSDVO_CMD_GET_MAX_TV_LUMA_FILTERSDVO_CMD_GET_AUDIO_ENCRYPT_PREFERDetected Composite TV connection Detected S-Video TV connection Detected Component TV connection Integrated TV is not present. <6>[drm] VGT interface version mismatch! <6>[drm] Virtual GPU for Intel GVT-g detected. <6>[drm] balloon space: range [ 0x%lx - 0x%lx ] %lu KiB. <6>[drm] VGT ballooning configuration: <6>[drm] Mappable graphic memory: base 0x%lx size %ldKiB <6>[drm] Unmappable graphic memory: base 0x%lx size %ldKiB Invalid ballooning configuration! <6>[drm] VGT balloon successfully &dev_priv->modeset_restore_locki915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s<6>[drm] This is an early pre-production Haswell machine. It may not be fully functional. failed to remove conflicting framebuffer drivers Failed to create our workqueue. Failed to create our dp workqueue. Failed to create our hangcheck workqueue. <6>[drm] Display disabled (module parameter) <6>[drm] Display fused off, disabling has subslice power gating: %s <6>[drm] failed to find VBIOS tables unregister_oom_notifier(&dev_priv->mm.oom_notifier)drivers/gpu/drm/i915/i915_dma.ctimeout disabling GT waking !HAS_RUNTIME_PM(dev)WARN_ON_ONCE(%s)Resuming device Device resumed KMS and UMS disabled. Failed to reset chip: %i Failed hw init on reset %d Found Ibex Peak PCH !IS_GEN5(dev)WARN_ON(%s)Found CougarPoint PCH Found PantherPoint PCH Found LynxPoint PCH Found LynxPoint LP PCH Found SunrisePoint PCH !IS_SKYLAKE(dev)Found SunrisePoint LP PCH Assuming Ibex Peak PCH Assuming CouarPoint PCH Assuming LynxPoint PCH Assuming SunrisePoint PCH No PCH found. offSuspending device Device suspended Suspend complete failed: %d dev: %p i915Intel Graphics20151010&dev_priv->pm_qosspurious interrupt CRC buffer overflowing I915_READ(SDEIER) != 0WARN_ON(%s)!intel_irqs_enabled(dev_priv)bits & ~maskWARN_ON_ONCE(%s)dev_priv->rps.pm_iirAudio CP request interrupt Audio CP change interrupt pipe %c FDI IIR: 0x%08x PCH poison interrupt Poison interrupt PCH HDCP audio interrupt Unexpected DE Misc interrupt Unexpected DE Port interrupt !mode->crtc_clockInvalid crtc %u crtc %u is disabled L3_PARITY_ERROR=1ROW=%dBANK=%dSUBBANK=%dSLICE=%d<3>i915: IPEIR: 0x%08x <3>i915: IPEHR: 0x%08x <3>i915: INSTPS: 0x%08x <3>i915: ACTHD: 0x%08x <3>i915: page table error <3>i915: PGTBL_ER: 0x%08x <3>i915: instruction error <3>i915: INSTPM: 0x%08x EIR stuck: 0x%08x, masking ERROR=1RESET=1ERROR=0resetting chip Kicking stuck wait on %sKicking stuck semaphore on %sno progressstuck<6>[drm] %s on %s Ring hung%x %u %d Resetting error state l3 parity sysfs setup failed RPS sysfs setup failed errorl3_parity_slice_1l3_paritygt_RP0_freq_mhzgt_RP1_freq_mhzgt_RPn_freq_mhzgt_act_freq_mhzgt_cur_freq_mhzgt_max_freq_mhzgt_min_freq_mhzvlv_rpe_freq_mhzrc6_enablerc6_residency_msrc6p_residency_msrc6pp_residency_msmedia_rc6_residency_msi915/skl_dmc_ver1.bini915/bxt_dmc_ver1.binLoading %s Finished loading %s CSR is not loaded. CSR SSP Base Not fine CSR HTP Not fine &dev_priv->rps.hw_lockLatency value missing offonEnabling RC6 states: RC6 %s ABFIFO size - (0x%08x) %s: %d FIFO watermark level: %ld plane->wm.fifo_size != 63WARN_ON(%s)fifo_size != 512 - 1flush pipe %c (pass %d) primaryspritePipe %c %s %c FIFO size: %d disabledenabledmemory self-refresh is %s val > dev_priv->rps.max_freqval < dev_priv->rps.min_freqOdd GPU freq value %s WM%d latency not provided GPLL not enabled noyesGPLL enabled? %s GPU status: 0x%08x <6>[drm] RC6 %s SKL Mailbox read error = %d DSPFW1 register is %x DSPFW3 register is %x self-refresh entries: %d fifo_left != 0htotal == 0level == 0 && wm > max_wmbad pxval: %ld !dev_priv->vlv_pctxinclude/drm/drm_gem.hPCBR: 0x%08x DDR speed: %d MHz max GPU freq: %d MHz (%u) RPe GPU freq: %d MHz (%u) min GPU freq: %d MHz (%u) Odd GPU freq values ips_link_to_i915_driverinclude/drm/drm_backport.hunknown fsb frequency 0x%04x Gen9 PlanePrimarySpriteCursor23p->pixel_rate == 0WARN_ON(!wm_changed) wm_lp != 1!r->enableDevice still suspended. WARN_ON(%s)!power_well->countdisabling %s enabling %s Initial PHY_CONTROL=0x%08x Interrupts not disabled yet. DC5 still not disabled. Disabling DC9 Power well on. Enabling DC9 &power_domains->lockctrl != statectrl << 16 != stateWARN_ON_ONCE(%s)power_well->data != PIPE_APG0 not enabled PG1 in disabled state Unknown power well %lu Disabling DC6 Enabling %s %s enable timeout Disabling %s CSR firmware not ready (%d) Runtime PM not enabled. Backlight is not disabled. Enabling DC6 Enabling DC5 Enabling power well Timeout enabling power well always-ondisplaypower well 1MISC IO power wellpower well 2DDI A/E power wellDDI B power wellDDI C power wellDDI D power welldpio-common-bcdpio-common-ddpio-tx-b-01dpio-tx-b-23dpio-tx-c-01dpio-tx-c-23dpio-commoni915_dpcdsize > sizeof(buf)WARN_ON(%s)%04x: %*ph %c %s noyesLLC: %s eLLC: %zuMB Current sequence (%s): %x gen: %d pch: %d is_mobile: %s is_i85x: %s is_i915g: %s is_i945gm: %s is_g33: %s need_gfx_hws: %s is_g4x: %s is_pineview: %s is_broadwater: %s is_crestline: %s is_ivybridge: %s is_valleyview: %s is_haswell: %s is_skylake: %s is_preliminary: %s has_fbc: %s has_pipe_cxsr: %s has_hotplug: %s cursor_needs_physical: %s has_overlay: %s overlay_needs_physical: %s supports_tv: %s has_llc: %s has_ddi: %s has_fpga_dbg: %s 10%02lx%lxnot supported GPU idle: %s IRQs disabled: %s Usage count: %d no ppgtt for context %d default context: context %d: Copied %d bytes from user Got %d for test active %llu 0x%llx 0x%08llx Use countPower well/domain%-25s %s %-25s %d PIPE_APIPE_BPIPE_CPIPE_A_PANEL_FITTERPIPE_B_PANEL_FITTERPIPE_C_PANEL_FITTERTRANSCODER_ATRANSCODER_BTRANSCODER_CTRANSCODER_EDPPORT_DDI_A_2_LANESPORT_DDI_A_4_LANESPORT_DDI_B_2_LANESPORT_DDI_B_4_LANESPORT_DDI_C_2_LANESPORT_DDI_C_4_LANESPORT_DDI_D_2_LANESPORT_DDI_D_4_LANESPORT_DDI_E_2_LANESPORT_DSIPORT_CRTPORT_OTHERVGAAUDIOPLLSAUX_AAUX_BAUX_CAUX_DGMBUSINIT %-23s %d WM%d %u (%u.%u usec) nonexisting DP port %c SizeEndStart%-15s%8s%8s%8s Pipe %c Plane%-8d%8u%8u%8u Cursor %-13s%8u%8u%8u DPLL%i: %s, id: %i tracked hardware state: dpll: 0x%08x dpll_md: 0x%08x fp0: 0x%08x fp1: 0x%08x wrpll: 0x%08x CRTC %d: eDP: DSI: HDMI: DP: Other encoder (id=%d). VBT: DRRS_type: Static VBT: DRRS_type: Seamless VBT: DRRS_type: None DRRS Supported: Yes Idleness DRRS: Disabled Busy_frontbuffer_bits: 0x%X DRRS_State: DRRS_HIGH_RR DRRS_State: DRRS_LOW_RR DRRS_State: Unknown(%d) Vrefresh: %d DRRS Supported : No No active crtc found pipeunknown object %s unknown pipe %s unknown source %s !IS_G4X(dev)stopping CRCs for pipe %c Stopping rings 0x%08llx Resetting error state Dropping caches: 0x%08llx Workarounds applied: %d OKFAIL%llubugDDC = 0x%08x DDC2 = 0x%08x C0DRB3 = 0x%04x C1DRB3 = 0x%04x MAD_DIMM_C0 = 0x%08x MAD_DIMM_C1 = 0x%08x MAD_DIMM_C2 = 0x%08x TILECTL = 0x%08x GAMTARBMODE = 0x%08x ARB_MODE = 0x%08x DISP_ARB_CTL = 0x%08x L-shaped memory detected enableddisabledself-refresh: %s Currently: unknown Currently: enabled Currently: disabled RPS enabled? %d GPU busy? %d CPU waiting? %d , active%s [%d]: %d boosts%s Semaphore boosts: %d%s MMIO flip boosts: %d%s Kernel boosts: %d GuC total action count: %llu GuC action failure count: %u GuC last action status: 0x%x GuC submissions: Total %s: %llu GuC execbuf client @ %p: Failed to queue: %u Failed doorbell: %u Last submission result: %d Submissions: %llu %s Total: %llu Display IER: %08x Display IIR: %08x Display IIR_RW: %08x Display IMR: %08x Pipe %c stat: %08x Port hotplug: %08x DPFLIPSTAT: %08x DPINVGTT: %08x GT Interrupt IMR %d: %08x GT Interrupt IIR %d: %08x GT Interrupt IER %d: %08x PCU interrupt mask: %08x PCU interrupt identity: %08x PCU interrupt enable: %08x Pipe %c power disabled Pipe %c IMR: %08x Pipe %c IIR: %08x Pipe %c IER: %08x Master IER: %08x Render IER: %08x Render IIR: %08x Render IMR: %08x PM IER: %08x PM IIR: %08x PM IMR: %08x Interrupt enable: %08x Interrupt identity: %08x Interrupt mask: %08x Pipe %c stat: %08x %s requests: %d %x @ %d: %s [%d] No requests SSEU Device Info Available Slice Total: %u Available EU Total: %u Has Slice Power Gating: %s Has EU Power Gating: %s SSEU Device Status Enabled Slice Total: %u Enabled Subslice Total: %u Enabled EU Total: %u Semaphores are disabled %s Last signal:0x%08llx (0x%02llx) Last wait: 0x%08x Sync seqno: 0x%08x %02x%02x%02x%02x%02x%02x PSR not supported Sink_Support: %s Source_OK: %s Enabled: %s Active: %s Re-enable work scheduled: %s HW Enabled & Active bit: %s pipe %cPerformance_Counter: %u PDP%d 0x%016llx GFX_MODE: 0x%08x PP_DIR_BASE: 0x%08x PP_DIR_BASE_READ: 0x%08x PP_DIR_DCLV: 0x%08x aliasing PPGTT: pd gtt offset: 0x%08x ECOCHK: 0x%08x proc: %s %s.wake_count = %u Status pointer: 0x%08X %d requests in queue Head request id: %u Head request tail: %u [k]batch pool gp*%x purgeable dirty] %x %x%s%s%s (name: %d) (pinned x %d) (display) (fence: %d)pp, type: %u)) (stolen: %08llx) (%s mappable) (%s) (frontbuffer: 0x%03x)HW context (default context %s) %s: %s cache[%d]: %d objects total: %d Total fences = %d unusedActive: Inactive: FBC enabled FBC disabled: %s Compressing: %s unsupported on this chipset %d %d %d GMCH temp: %ld Chipset power: %ld GFX power: %ld Total power: %ld Video Turbo Mode: %s Turbo enabled: %s HW control enabled: %s SW control enabled: %s RC6 Enabled: %s DownUpRender Power Well: %s Media Power Well: %s RC information accurate: %s RC1e Enabled: %s Deep RC6 Enabled: %s Deepest RC6 Enabled: %s Current RC state: Core Power Down on RC3 RC6 RC7 Unknown Core Power Down: %s RC6 residency since boot: %u RC6 voltage: %dmV RC6+ voltage: %dmV RC6++ voltage: %dmV HD boost: %s Boost freq: %d Gated voltage change: %s Starting frequency: P%d Max P-state: P%d Min P-state: P%d RS1 VID: %d RS2 VID: %d Render standby enabled: %s Current RS state: RC1 RC1E RS1 RS2 (RC6) RC3 (RC6+) unknown Hangcheck disabled Hangcheck inactive %s: seqno = %x [current %x] max ACTHD = 0x%08llx score = %d action = %d Requested P-state: %d Requested VID: %d Current VID: %d Current P-state: %d GT_PERF_STATUS: 0x%08x Render p-state ratio: %d Render p-state VID: %d Render p-state limit: %d RPSTAT1: 0x%08x RPMODECTL: 0x%08x RPINCLIMIT: 0x%08x RPDECLIMIT: 0x%08x RPNSWREQ: %dMHz CAGF: %dMHz RP CUR UP EI: %dus RP CUR UP: %dus RP PREV UP: %dus Up threshold: %d%% RP CUR DOWN EI: %dus RP CUR DOWN: %dus RP PREV DOWN: %dus Down threshold: %d%% Current freq: %d MHz Actual freq: %d MHz Idle freq: %d MHz Min freq: %d MHz Max freq: %d MHz DDR freq: %d MHz actual GPU freq: %d MHz current GPU freq: %d MHz max GPU freq: %d MHz min GPU freq: %d MHz idle GPU freq: %d MHz no P-state info available GuC firmware status: path: %s fetch: %s load: %s version wanted: %d.%d version found: %d.%d GuC status 0x%08x: Bootrom status = 0x%x uKernel status = 0x%x MIA Core status = 0x%x Scratch registers: %2d: 0x%x Stall check enabled, %d prepares MMIO update completed? %d Stolen: %u objects, %zu bytes %llu [%llu] gtt total i915_forcewake_user%8u %8x %8x %8x %8x %8x fixed mode: CRTC info --------- primary plane disabled , mode: Connector info -------------- name: %s subpixel order: %s CEA rev: %d DPCD rev: %x audio support: %s modes: 0x%08x 0x%08x 0x%08x 0x%08x CONTEXT: %s %u Not bound in GGTT page == NULLi915_capabilitiesi915_gem_objectsi915_gem_gtti915_gem_pinnedi915_gem_activei915_gem_inactivei915_gem_stoleni915_gem_pageflipi915_gem_requesti915_gem_seqnoi915_gem_fence_regsi915_gem_interrupti915_gem_hwsi915_gem_hws_blti915_gem_hws_bsdi915_gem_hws_veboxi915_gem_batch_pooli915_guc_infoi915_guc_load_statusi915_guc_log_dumpi915_frequency_infoi915_hangcheck_infoi915_drpc_infoi915_emon_statusi915_ring_freq_tablei915_frontbuffer_trackingi915_fbc_statusi915_ips_statusi915_sr_statusi915_opregioni915_gem_framebufferi915_context_statusi915_dump_lrci915_execlistsi915_forcewake_domainsi915_swizzle_infoi915_ppgtt_infoi915_llci915_edp_psr_statusi915_sink_crc_eDP1i915_energy_uJi915_runtime_pm_statusi915_power_domain_infoi915_display_infoi915_semaphore_statusi915_shared_dplls_infoi915_dp_mst_infoi915_wa_registersi915_ddb_infoi915_sseu_statusi915_drrs_statusi915_rps_boost_infoi915_pipe_A_crci915_pipe_B_crci915_pipe_C_crci915_wedgedi915_max_freqi915_min_freqi915_cache_sharingi915_ring_stopi915_ring_missed_irqi915_ring_test_irqi915_gem_drop_cachesi915_error_statei915_next_seqnoi915_display_crc_ctli915_pri_wm_latencyi915_spr_wm_latencyi915_cur_wm_latencyi915_fbc_false_colori915_dp_test_datai915_dp_test_typei915_dp_test_activenoneplane1plane2pfTVDP-BDP-CDP-DautoXYbit9bit9/bit10bit9/bit11bit9/bit10/bit11unknownbit9/bit17bit9/bit10/bit17Failed to vmap pages WARN_ON(%s)CMD: Failed to vmap batch CMD: Failed to copy batch !hash_empty(ring->cmd_hash)CMD: cmd_parser_init failed! WARN_ON(%s)include/drm/drm_gem.hi915.enable_execlistsWARN_ON(%s)L3 remapping failed ring init context: %d HW context %d destroyed retinclude/drm/drm_gem.hCouldn't pin %d PPGTT setup failed (%ld) HW context %d created LRfakeHWi915WARN_ON(%s)!list_empty(&vm->active_list)i915_vma_unbind(vma)!list_empty(&vma->exec_list)include/drm/drm_gem.hWARN_ON(%s)Failed to lookup VMA include/drm/drm_gem.h%s didn't clear reload no rel constants on pre-gen4 sol reset is gen7/rcs only include/linux/io-mapping.hexecbuf with %d buffers RS is not available on %s Could not create LRC %u: %d execbuf2 with %d buffers dirty rvsd2 field WARN_ON(%s)!obj->map_and_fenceablefence->pin_countflags == 0WARN_ON(%s)PG!viewGMADR size = %lldM GTT stolen size = %zdM ppgtt mode: %i Scratch setup failed Unknown GMADR size (%llx) !p->pagefailed to set up gmch px_dma(vm->scratch_page) == 0!pdp!pdp->page_directory[pdpe]!pd->page_table[pde]!px_page(pt) PDE: %x 0x%lx [%03d,%04d]: = %08x SCRATCH PDPE #%d 0x%llx [%03d,%03d,%04d]: = %llx PML4E #%llu !pdp->page_directory[i]!pd->page_table[i]!ppgtt->pml4.pdps[i]Couldn't idle GPU PPGTTGGTT!USES_FULL_48BIT_PPGTT(dev)!bitmap_empty(new_pds, pdpes)Adding PPGTT at offset %x i915_gem_obj_ggtt_bound(obj)Reservation failed: %i include/drm/drm_mm.hstart + length < startstart + length > vm->totalpt == vm->scratch_pt!pd!pt!pd_lenWARN_ON(%s)ppgttglobalinclude/drm/drm_gem.h i915_gem_objecti915_gem_vmai915_gem_request&dev_priv->fb_tracking.lockvma->node.allocatedinclude/linux/scatterlist.h!ctxrequest == NULLemit|add_request failed: %d! no view specifiedinclude/drm/drm_backport.hvma->pin_count == 0obj->pin_display == 0PPGTT enable HW failed %d (ignored)!ring->default_contextallow wake ack timed out dev_priv->mm.busyIRQs disabled*timeout < 0!ring->irq_get(ring)bytes != sizeret != -EIOret == -ERESTARTSYSi915_vma_unbind(vma)obj->frontbuffer_bitsobj->pages_pin_count!to_reqggtt!ggtt_viewmappabletotalinclude/linux/io-mapping.hinclude/drm/drm_gem.hring->id != RCSWARN_ON(%s)only %d relocs resolved include/drm/drm_gem.hoffset=0x%x, size=%d &dev_priv->mm.stolen_lockGraphics Stolen MemoryWARN_ON(%s)size == 0size & 4095stolen_offset & 4095include/drm/drm_gem.hunknown tiling mode include/drm/drm_gem.hinclude/drm/drm_backport.h&dev_priv->mm_lockinclude/drm/drm_backport.hinclude/drm/drm_gem.h L3+LLC uncached snooped LLC WTinclude/linux/io-mapping.hWARN_ON(%s)overflow %s [%d]: %02x ] %02x P p dirty purgeable userptr (name: %d) (fence: %d) %08x : %08x no error state collected %s Time: %ld s %ld us Kernel: 2.6.32-642.el6.i686 Reset count: %u Suspend count: %u PCI ID: 0x%04x IOMMU enabled?: %d EIR: 0x%08x IER: 0x%08x GTIER gt %d: 0x%08x GTIER: 0x%08x PGTBL_ER: 0x%08x FORCEWAKE: 0x%08x DERRMR: 0x%08x CCID: 0x%08x Missed interrupts: 0x%08lx fence[%d] = %08llx INSTDONE_%d: 0x%08x ERROR: 0x%08x DONE_REG: 0x%08x ERR_INT: 0x%08x %s command stream: START: 0x%08x HEAD: 0x%08x TAIL: 0x%08x CTL: 0x%08x HWS: 0x%08x ACTHD: 0x%08x %08x IPEIR: 0x%08x IPEHR: 0x%08x INSTDONE: 0x%08x BBADDR: 0x%08x %08x BB_STATE: 0x%08x INSTPS: 0x%08x INSTPM: 0x%08x FADDR: 0x%08x %08x RC PSMI: 0x%08x FAULT_REG: 0x%08x GFX_MODE: 0x%08x PDP%d: 0x%016llx PP_DIR_BASE: 0x%08x seqno: 0x%08x noyes waiting: %s ring->head: 0x%08x ring->tail: 0x%08x unknown hangcheck: %s [%d] vm[%d] ActivePinned (submitted by %s [%d])%s --- %d requests %s --- ringbuffer = 0x%08x %s --- HW Status = 0x%08llx [%04x] %08x %08x %08x %08x %s --- HW Context = 0x%08x Semaphore page = 0x%08x GPU HANG: ecode %d:%d:0x%08x, in %s [%d]continuereset, reason: %s, action: %s<6>[drm] %s renderbsdbltveboxbsd2 X Yidlewaitactiveactive (loop)kickhung1WARN_ON_ONCE(%s)i915_pipe_update_start%s: i915_pipe_update_endi915_gem_object_createobj=%p, size=%u i915_gem_shrinkdev=%d, target=%lu, flags=%x i915_vma_bind, mappablei915_vma_unbindi915_va_allocvm=%p (%s), 0x%llx-0x%llx i915_page_table_entry_alloci915_page_table_entry_mapi915_gem_object_change_domaini915_gem_object_pwriteobj=%p, offset=%u, len=%u i915_gem_object_preadi915_gem_object_fault, writableCPUGTTobj=%p, %s index=%u %s obj=%p i915_gem_object_clflushi915_gem_object_destroyi915_gem_evictdev=%d, size=%d, align=%d %s i915_gem_evict_everythingdev=%d i915_gem_evict_vmdev=%d, vm=%p i915_gem_ring_sync_toi915_gem_ring_dispatchi915_gem_ring_flushdev=%u, ring=%u, seqno=%u i915_gem_request_addi915_gem_request_retirei915_gem_request_completei915_gem_request_wait_endi915_gem_request_notifyi915_gem_request_wait_beginnoyes (NB)i915_flip_requestplane=%d, obj=%p i915_flip_completeintel_gpu_freq_changenew_freq=%u dev=%u, vm=%p i915_ppgtt_createi915_ppgtt_releasedev=%u, ctx=%p, ctx_vm=%p i915_context_createi915_context_freeswitch_mmpipeenum pipeframeu32scanlineminmaxobjstruct drm_i915_gem_object *sizedevinttargetunsigned longflagsunsignedvmstruct i915_address_space *offsetu64startendname__data_loc char[]pxpdefirstlastcur_ptesread_domainswrite_domainlenindexgttboolwritealignsync_fromsync_toseqnoringinvalidateflushblockingplanefreqctxstruct intel_context *to%*pbWARN_ON(%s)i915WARN_ON(%s)i915.enable_ppgtt == -1lrca & 0xFFFFFFFF00000FFFULL!intel_irqs_enabled(dev_priv)Never submitted head request req == NULLringbuf->reserved_in_useinclude/drm/drm_gem.hctx->engine[ring->id].stateCould not set to CPU domain Could not get object pages Failed to populate LRC: %d ring create req: %d ring init context: %d w->count == 0WARN_ON_ONCE(%s)sol reset is gen7 only Execlists enabled for %s req1 && req1->elsp_submittedrender ringring->id != RCSbsd ringblitter ringvideo enhancement ringbds2 ringWARN_ON(%s)!ringbuf->reserved_in_useWARN_ON(%s)ringbuf->reserved_in_useringbuf->reserved_sizeidx >= I915_MAX_WA_REGSinclude/drm/drm_gem.h!intel_irqs_enabled(dev_priv)req == NULLring->id != RCSring->scratch.objring->buffer%s hws offset: 0x%08x video enhancement ringblitter ringbsd2 ringbsd ringinit render state: %d render ring!dev_priv->semaphore_objFailed to allocate batch bo Failed to ping batch bo Device suspended GT wake FIFO error 0x%x WARN_ON(%s)writing toreadingafterbeforedomain->wake_countidunknownd->wake_countd->reg_set == 0domain->wake_count == 0dev_priv->pm.suspended!fw_domainsactive_domains%s: reset request timeout <6>[drm] Found %zuMB of eLLC renderblittermediaUNKNOWN!i915/skl_guc_ver4.bininclude/drm/drm_gem.hreturning %d GuC fw fetch status %s set-domain failed %d pin failed %d GUC: unsupported core family SUCCESSFAILNONEPENDINGlen < 1 || len > 15WARN_ON(%s)include/drm/drm_gem.hdesc.engines_used == 0(value & GEN8_DRB_VALID) != 0wq_off & 3normalhighacomp->ops || acomp->devWARN_ON(%s)Disable audio codec ELD size %d %s: crtc is NULL no pipe for the port %c pipe %c connects port %c port == PORT_A!HAS_DDI(dev_priv)WARN_ON_ONCE(%s)invalid port: %d no suitable N value is found WARN_ON(%s)CRTCPLANE*scaler_id < 0Cannot find scaler for %s:%d Unknown plane property '%s' !drm_crtc_stateWARN_ON(%s)VBT header incomplete $VBTVBT invalid signature BDB header incomplete BDB incomplete Using VBT from %s: %20s Set default to SSC at %d kHz OpRegionPCI ROMcrt_ddc_bus_pin: %d VBT initial LVDS value %x highlowIncorrect SDVO port. Skip it SDVOBSDVOCFound MIPI as LFP DRRS State Enabled:%d No PSR BDB found. No MIPI config BDB foundFound MIPI sequence block Found mipi sequence - %d undefined sequence Unknown element Port %c is analog Port %c is TMDS compatible Port %c is internal DP ThinkCentre A57Num Pipes: %d PWR_WELL_CTL2: %08x Pipe [%d]: offon Power: %s SRC: %08x STAT: %08x Plane [%d]: CNTR: %08x STRIDE: %08x SIZE: %08x POS: %08x ADDR: %08x SURF: %08x TILEOFF: %08x Cursor [%d]: BASE: %08x CPU transcoder: %c CONF: %08x HTOTAL: %08x HBLANK: %08x HSYNC: %08x VTOTAL: %08x VBLANK: %08x VSYNC: %08x Unsupported divider value failed to read control word failed to write control word HPLL VCO %u kHz enabling CxSR downclocking disabling CxSR downclocking Max CD clock rate: %d kHz Max dotclock rate: %d kHz num_connectors == 0WARN_ON(%s)Unknown cd freq selection !crtc_state->base.statedisen%sabling fdi C rx for crtc_state = %p !encoder->crtcwas_visiblevisible!HAS_DDI(dev)WARN_ON_ONCE(%s)!HAS_PCH_SPLIT(dev)!ctx!statecpu_transcoder: %c pipe bpp: %i, dithering: %i audio: %i, infoframes: %i requested mode: adjusted mode: port clock: %d pipe src size: %dx%d disabledenabledips: %i double wide: %i planes on this crtc STANDARDCURSORIncorrect port type FDI_RX_IIR 0x%x FDI train 1 done, level %i. FDI train 2 done, level %i. FDI train done. FDI train 1 done. FDI train 1 fail! FDI train 2 done. FDI train 2 fail! FDI train done HAS_DDI(dev)pll->active == 0!pll->ondisabling %s pll == NULLpll->config.crtc_mask == 0pll->onenabling %s Failed to write to D_COMP invalid cdclk frequency Switching to FCLK failed unsupported CDCLK freq %dDBuf power disable timeout! Display already initialized DBuf power enable timeout! DPLL %d failed to lock DBuf power disable timeout Couldn't disable DPLL0 %s change in progress cdclkfailed to alloc fb obj == NULLPLL %d failed to lock buffer is too small cursor cannot be tiled No Y tiling for legacy addfb Unsupported tiling 0x%llx! lineartiledunsupported pixel format: %s framebuffer init failed %d no such CRTC id !in_interrupt()Changing CDCLK to %dKHz DBuf power enable timeout DPLL0 not locked shared_dpll[i].crtc_mask!encoderCRTC:%d allocated %s using %s for pipe %c Unexpected PCH type %d Removing stuck page flip retx != src_x || y != src_y!dst_w || !dst_hintel_fb_obj(old_fb) == NULLinclude/drm/drm_backport.hfailed to attach phys object disabling pipe %c pipe_off wait timed out enabling pipe %c intel_crtc->active!pll->config.crtc_masksetting up %s !state->allow_modeset[CONNECTOR:%d:%s] [ENCODER:%d:%s] [CRTC:%d] pipe state doesn't match! [hw state][sw state]%s pll hw state mismatch LP PCH doesn't have FDI Using SSC on panel Using SSC on eDP Disabling SSC entirely Disabling package C8+ LCPLL not locked yet Enabling package C8+ CRTC for pipe %c enabled Power well on <6>[drm] Power well on SPLL enabled <6>[drm] SPLL enabled WRPLL1 enabled <6>[drm] WRPLL1 enabled WRPLL2 enabled <6>[drm] WRPLL2 enabled Panel power on <6>[drm] Panel power on CPU PWM1 enabled <6>[drm] CPU PWM1 enabled CPU PWM2 enabled <6>[drm] CPU PWM2 enabled PCH PWM1 enabled <6>[drm] PCH PWM1 enabled Utility pin enabled <6>[drm] Utility pin enabled PCH GTC enabled <6>[drm] PCH GTC enabled IRQs enabled <6>[drm] IRQs enabled LCPLL still locked !target_freqinclude/drm/drm_gem.hEncoder config failure CRTC fixup failed [fastset][modeset]include/drm/drm_crtc.h!connector_state->crtccrtc->active[setup_hw_state]put_domainsintel fb init failed initial plane fb obj %p &dev_priv->pps_mutexs%d display pipe%s available. czclkCZ clock rate: %d kHz probing SDVOB probing HDMI on SDVOB probing SDVOC probing HDMI on SDVOC NCR CorporationPCH DPLL APCH DPLL B&dev_priv->fbc.lockFBC idle timed out disabled FBC enabled fbc on plane %c unsupported by this chipsetno outputnot enough stolen memoryFBC unsupported on planemore than one pipe activedisabled per module paramdisabled per chip defaultrotation unsupportedKernel debugger is activepixel rate is too bigpixel format is invalidunknown reasonDisabling FBC: %s WARN_ON(%s)stride < 512(stride & (64 - 1)) != 0<6>[drm] pipe %c underrun WARN_ON(%s)WARN_ON(%s)shortlongdigital hpd port %c - %s Broadcast RGBaudioAutomaticFullLimited 16:235force-dvioffautoon Register file at 0x%08lx: OBUF_0Y: 0x%08x OBUF_1Y: 0x%08x OBUF_0U: 0x%08x OBUF_0V: 0x%08x OBUF_1U: 0x%08x OBUF_1V: 0x%08x OSTRIDE: 0x%08x YRGB_VPH: 0x%08x UV_VPH: 0x%08x HORZ_PH: 0x%08x INIT_PHS: 0x%08x DWINPOS: 0x%08x DWINSZ: 0x%08x SWIDTH: 0x%08x SWIDTHSW: 0x%08x SHEIGHT: 0x%08x YRGBSCALE: 0x%08x UVSCALE: 0x%08x OCLRC0: 0x%08x OCLRC1: 0x%08x DCLRKV: 0x%08x DCLRKM: 0x%08x SCLRKVH: 0x%08x SCLRKVL: 0x%08x SCLRKEN: 0x%08x OCONFIG: 0x%08x OCMD: 0x%08x OSTART_0Y: 0x%08x OSTART_1Y: 0x%08x OSTART_0U: 0x%08x OSTART_0V: 0x%08x OSTART_1U: 0x%08x OSTART_1V: 0x%08x OTILEOFF_0Y: 0x%08x OTILEOFF_1Y: 0x%08x OTILEOFF_0U: 0x%08x OTILEOFF_0V: 0x%08x OTILEOFF_1U: 0x%08x OTILEOFF_1V: 0x%08x FASTHSCALE: 0x%08x UVSCALEV: 0x%08x include/linux/io-mapping.hdev_priv->overlayWARN_ON(%s)include/drm/drm_gem.huserspace bug: no overlay !objdev_priv->overlay->activeinclude/drm/drm_backport.hoverlay->last_flip_req!overlay->activeoverlay->activeoverlay underrun, DOVSTA: %x &dev_priv->psr.lockWARN_ON(%s)dev_priv->psr.active!(val & EDP_PSR_ENABLE)PSR already in use HSW ties PSR to DDI A (eDP) PSR disable by flag WARN_ON(%s)writereadWrong plane <-> crtc mapping WARN_ON(%s)!can_scale_DSMfailed to evaluate _DSM: %d MUX info connectors: %lld Connector id: 0x%016llx bad type port id: %s display mux info: %s aux/dc mux info: %s hpd mux info: %s ReservedAnalog VGALVDSHDMI/DVI_BHDMI/DVI_CHDMI/DVI_DDisplayPort_ADisplayPort_BDisplayPort_CDisplayPort_DWiDiunknownNo MUX, iGPU onlyNo MUX, dGPU onlyMUXed between iGPU and dGPUSWSCI request timed out SWSCI request error %u ACPI OpRegion not supported! IntelGraphicsMemopregion signature mismatch SWSCI supported ASLE supported Illum is not supported bclp = 0x%08x Pfit is not supported PWM freq is not supported SROT is not supported ISCT is not supported videoWARN_ON(%s)No ACPI video bus found _ADR%d outputs detected failed to restore crtc mode state != FBINFO_STATE_RUNNINGWARN_ON(%s)!encoder->crtciEnabled: %i, detected: %i pipe %c not active, skipping !intel_fb->objfailed to pin obj: %d include/drm/drm_gem.hre-using BIOS fb inteldrmfbCH7017_LVDS_CONTROL_2: %02x CH7017_OUTPUTS_ENABLE: %02x CH7017_LVDS_POWER_DOWN: %02x Registers after mode setting ch7018ch7019ch7017%s detected on %s, addr %d %02X: %02X CH7011CH7010BCH7009ACH7009BCH7301CH7XXXVR00: 0x%04x VR01: 0x%04x VR10: 0x%04x VR30: 0x%04x VR40: 0x%04x VR80: 0x%04x VR81: 0x%04x VR82: 0x%04x VR83: 0x%04x VR84: 0x%04x VR85: 0x%04x VR86: 0x%04x VR87: 0x%04x VR88: 0x%04x VR8E: 0x%04x VR8F: 0x%04x Resetting the IVCH registers SIL164_FREQ_LO: 0x%02x SIL164_FREQ_HI: 0x%02x SIL164_REG8: 0x%02x SIL164_REG9: 0x%02x SIL164_REGC: 0x%02x TFP410_REV: 0x%02X TFP410_CTL1: 0x%02X TFP410_CTL2: 0x%02X TFP410_CTL3: 0x%02X TFP410_USERCFG: 0x%02X TFP410_DE_DLY: 0x%02X TFP410_DE_CTL: 0x%02X TFP410_DE_TOP: 0x%02X TFP410_DE_CNT: 0x%02X%02X TFP410_DE_LIN: 0x%02X%02X TFP410_H_RES: 0x%02X%02X TFP410_V_RES: 0x%02X%02X crt adpa set to 0x%x [CONNECTOR:%d:%s] force=%d CRT detected via hotplug CRT not detected via hotplug starting load-detect on CRT ACER ZGBDELL XPS 8700Invalid I_boost value %u bad wrpll refclk WARN_ON(%s)FDI link training failed! Invalid DDI encoder type %d dpll != SKL_DPLL0PLL %d not locked DPLL %d not locked timeout waiting for PHY1 GRC WRPLL 1WRPLL 2SPLLLCPLL1 is disabled CDCLK source is not LCPLL LCPLL is disabled bad spll freq bad port clock sel Unsupported link rate dpll == DPLL_ID_PRIVATEIncorrect PDiv Incorrect KDiv best_clock.m1 != 2Invalid VCO DPLL 1DPLL 2DPLL 3PORT PLL APORT PLL BPORT PLL C %d can't find connector failed to allocate vcpi failed to update payload %d Sink OUI: %02hx%02hx%02hx Branch OUI: %02hx%02hx%02hx Sink is MST capable Sink is not MST capable disableenableHAS_DDI(dev)WARN_ON(%s) k >= DP_MAX_SUPPORTED_RATESlen <= 0!IS_VALLEYVIEW(dev)!is_edp(intel_dp)pipes == 0intel_dp->want_panel_vddTurning eDP port %c VDD off dp pll off, should be on eDP PLL enable for clock %d dp pll on, should be off Panel doesn't support DRRS dev_priv->drrs.dpDRRS already enabled Wait complete eDP port %c VDD not forced on[CONNECTOR:%d:%s] no scaling not supported DRRS not supported. Unsupported refreshrate type Using signal levels %08x Using vswing level %d Using pre-emphasis level %d common_len <= 0failed to get link status clock recovery OK clock recovery not ok, resetfailed to train DP, aborting got esi %3ph got esi2 %3ph , %s%dsource rates: %s sink rates: %s common rates: %s DPCD: %*ph Detected EDP PSR Panel. not supportedsupportedPSR2 %s on sinkyesnoLINK_TRAINING test requested TEST_PATTERN test requested EDID test requested PHY_PATTERN test requested Invalid test request '%02x' DPeDPDPDDC-ADPDDC-BDPDDC-CDPDDC-DDPDDC-Eregistering %s bus for %s &dev_priv->drrs.mutexVBT doesn't support DRRS shortlonggot hpd irq on port %c - %s Wait for panel power cycle Turning eDP port %c VDD on Status 0x%08x Control 0x%08x txsize > 20rxsize > 20Wait for panel power on dp_reg & DP_PORT_ENEnabling DP audio on pipe %c MODE_NO_DBLESCAN no fixed mode drm_mode_duplicate failed no device found DPI FIFOs are not empty DSI LP not going Low pipe %c Starting MIPI sequence - %s Burst mode target is not set disabledenabledEot %s Clockstop %s videocommandMode %s Dual link: NONE Pixel Format %d TLPX %d LP RX Timeout 0x%x Turnaround Timeout 0x%x Init Count 0x%x HS to LP Count 0x%x LP Byte Clock %d DBI BW Timer 0x%x LP to HS Clock Count 0x%x HS to LP Clock Count 0x%x BTA %s no dsi device for port %c UNDEFINEDMIPI_SEQ_ASSERT_RESETMIPI_SEQ_INIT_OTPMIPI_SEQ_DISPLAY_ONMIPI_SEQ_DISPLAY_OFFMIPI_SEQ_DEASSERT_RESET DSI CLK Out of Range dsi_calc_mnp failed dsi pll div %08x, ctrl %08x DSI PLL locked DSI PLL lock failed Invalid BPP(0) Calculated pclk=%u wrong P1 divisor wrong m_seed programmed [CONNECTOR:%d:%s] sil164ch7xxxivchtfp410ch7017ns2501WARN_ON(%s)unknown info frame type %d !crtc->config->has_hdmi_sink[CONNECTOR:%d:%s] Live status not up!IS_BROXTON(dev_priv)couldn't fill AVI infoframe Integrated gfxIntelcouldn't fill SPD infoframe disenWARN_ON(%s)&dev_priv->gmbus_mutexi915 gmbus %sdpbdpcmiscdpdvgasscpanelno scaling not supported [CONNECTOR:%d:%s] disable LVDS for eDP support LVDS is not present in VBT using mode from VBT: using current (BIOS) mode: singledualCan't support LVDS on pipe A Apple Mac Mini (Core series)MSI IM-945GSE-ADell Studio HybridDell OptiPlex FX170AOpen Mini PCAOpen Mini PC MP915AOpen i915GMm-HFSAOpen i45GMx-IAopen i945GTt-VFAClientron U800Clientron E830Asus EeeBox PC EB1007Asus AT5NM10T-IHewlett-Packard HP t5740Hewlett-Packard t5745Hewlett-Packard st5747MSI Wind Box DC500Gigabyte GA-D525TUDSupermicro X7SPA-HFujitsu Esprimo Q900Intel D410PTIntel D425KTIntel D510MOIntel D525MWApple MacBook Pro 15" (2010)Apple MacBook Pro 15" (2011)Apple MacBook Pro 15" (2012)Toshiba Tecra A11source_min > source_maxWARN_ON(%s)target_min > target_maxpanel->backlight.max == 0bad panel fit mode: %d set backlight PWM = %d backlight already enabled util pin already enabled get backlight PWM = %d panel->backlight.deviceintel_backlightno backlight present per VBT !panel->backlight.setupdisabledenabledpipe %c %02X (%s)(%02X)SDVOCSDVOB%s: W: %02X %s I2c transfer returned %d I2c transfer returned %d/%d i2c transfer returned %d (??? %d) %02X%s: R: %s %s: R: ... failed [CONNECTOR:%d:%s] SDVO response %d %d [%x] initialising DVI device %d No enhancement is supported left_marginright_margintop_marginbottom_marginhposvpossaturationcontrasthuesharpnessbrightnessflicker_filterflicker_filter_adaptiveflicker_filter_2dtv_chroma_filtertv_luma_filterdot_crawldot crawl: current %d initialising TV type %d modeinitialising LVDS device %d SDVO DDC proxyNo SDVO device found on %s failed to retrieve SDVO DTD forcing bpc to 8 for SDVO couldn't fill AVI infoframe SDVO_CMD_RESETSDVO_CMD_GET_DEVICE_CAPSSDVO_CMD_GET_FIRMWARE_REVSDVO_CMD_GET_TRAINED_INPUTSSDVO_CMD_GET_ACTIVE_OUTPUTSSDVO_CMD_SET_ACTIVE_OUTPUTSSDVO_CMD_GET_IN_OUT_MAPSDVO_CMD_SET_IN_OUT_MAPSDVO_CMD_GET_HOT_PLUG_SUPPORTSDVO_CMD_SET_ACTIVE_HOT_PLUGSDVO_CMD_GET_ACTIVE_HOT_PLUGSDVO_CMD_SET_TARGET_INPUTSDVO_CMD_SET_TARGET_OUTPUTSDVO_CMD_GET_CLOCK_RATE_MULTSDVO_CMD_SET_CLOCK_RATE_MULTSDVO_CMD_GET_TV_FORMATSDVO_CMD_SET_TV_FORMATSDVO_CMD_GET_POWER_STATESDVO_CMD_GET_MAX_HPOSSDVO_CMD_GET_HPOSSDVO_CMD_SET_HPOSSDVO_CMD_GET_MAX_VPOSSDVO_CMD_GET_VPOSSDVO_CMD_SET_VPOSSDVO_CMD_GET_MAX_SATURATIONSDVO_CMD_GET_SATURATIONSDVO_CMD_SET_SATURATIONSDVO_CMD_GET_MAX_HUESDVO_CMD_GET_HUESDVO_CMD_SET_HUESDVO_CMD_GET_MAX_CONTRASTSDVO_CMD_GET_CONTRASTSDVO_CMD_SET_CONTRASTSDVO_CMD_GET_MAX_BRIGHTNESSSDVO_CMD_GET_BRIGHTNESSSDVO_CMD_SET_BRIGHTNESSSDVO_CMD_GET_MAX_OVERSCAN_HSDVO_CMD_GET_OVERSCAN_HSDVO_CMD_SET_OVERSCAN_HSDVO_CMD_GET_MAX_OVERSCAN_VSDVO_CMD_GET_OVERSCAN_VSDVO_CMD_SET_OVERSCAN_VSDVO_CMD_GET_FLICKER_FILTERSDVO_CMD_SET_FLICKER_FILTERSDVO_CMD_GET_MAX_SHARPNESSSDVO_CMD_GET_SHARPNESSSDVO_CMD_SET_SHARPNESSSDVO_CMD_GET_DOT_CRAWLSDVO_CMD_SET_DOT_CRAWLSDVO_CMD_GET_TV_CHROMA_FILTERSDVO_CMD_SET_TV_CHROMA_FILTERSDVO_CMD_GET_TV_LUMA_FILTERSDVO_CMD_SET_TV_LUMA_FILTERSDVO_CMD_GET_SUPP_ENCODESDVO_CMD_GET_ENCODESDVO_CMD_SET_ENCODESDVO_CMD_SET_PIXEL_REPLISDVO_CMD_GET_PIXEL_REPLISDVO_CMD_GET_COLORIMETRY_CAPSDVO_CMD_SET_COLORIMETRYSDVO_CMD_GET_COLORIMETRYSDVO_CMD_SET_AUDIO_STATSDVO_CMD_GET_AUDIO_STATSDVO_CMD_GET_HBUF_INDEXSDVO_CMD_SET_HBUF_INDEXSDVO_CMD_GET_HBUF_INFOSDVO_CMD_GET_HBUF_AV_SPLITSDVO_CMD_SET_HBUF_AV_SPLITSDVO_CMD_GET_HBUF_TXRATESDVO_CMD_SET_HBUF_TXRATESDVO_CMD_SET_HBUF_DATASDVO_CMD_GET_HBUF_DATAPower onSuccessNot supportedInvalid argPendingTarget not specifiedScaling not supportedNTSC_MNTSC_JNTSC_443PAL_BPAL_DPAL_GPAL_HPAL_IPAL_MPAL_NPAL_NCPAL_60SECAM_BSECAM_DSECAM_GSECAM_KSECAM_K1SECAM_LSECAM_60forcing bpc to 8 for TV [CONNECTOR:%d:%s] force=%d TV detected: %x, %x Unrecognised TV connection NTSC-MNTSC-443NTSC-JPAL-MPAL-NPAL480p576p720p@60Hz720p@50Hz1080i@50Hz1080i@60Hz640x480800x6001024x7681280x1024848x4801280x7201920x1080VGT deballoon. VGT balloon fail Unknown parameter %d copy_to_user failed &dev_priv->backlight_lock&dev_priv->sb_lock&dev_priv->csr_lock&dev_priv->av_mutexhas_fpga_dbg,has_ddi,has_llc,supports_tv,overlay_needs_physical,has_overlay,cursor_needs_physical,has_hotplug,has_pipe_cxsr,has_fbc,is_preliminary,is_skylake,is_haswell,is_valleyview,is_ivybridge,is_crestline,is_broadwater,is_pineview,is_g4x,need_gfx_hws,is_g33,is_i945gm,is_i915g,is_i85x,is_mobile,bridge device not found failed to map registers inteldrmfbi915i915-dpi915-hangchecki915 MCHBARfailed bus alloc: %d slice total: %u subslice total: %u subslice per slice: %u EU total: %u EU per subslice: %u nyhas slice power gating: %s has EU power gating: %s failed to init modeset WARN_ON(%s)<6>i915: switched on <3>i915: switched off failed to idle hardware: %d I915_INITI915_FLUSHI915_FLIPI915_BATCHBUFFERI915_IRQ_EMITI915_IRQ_WAITI915_GETPARAMI915_SETPARAMI915_ALLOCI915_FREEI915_INIT_HEAPI915_CMDBUFFERI915_DESTROY_HEAPI915_SET_VBLANK_PIPEI915_GET_VBLANK_PIPEI915_VBLANK_SWAPI915_HWS_ADDRI915_GEM_INITI915_GEM_EXECBUFFERI915_GEM_PINI915_GEM_UNPINI915_GEM_BUSYI915_GEM_THROTTLEI915_GEM_ENTERVTI915_GEM_LEAVEVTI915_GEM_CREATEI915_GEM_PREADI915_GEM_PWRITEI915_GEM_MMAPI915_GEM_SET_DOMAINI915_GEM_SW_FINISHI915_GEM_SET_TILINGI915_GEM_GET_TILINGI915_GEM_GET_APERTUREI915_GEM_MMAP_GTTI915_GET_PIPE_FROM_CRTC_IDI915_GEM_MADVISEI915_OVERLAY_PUT_IMAGEI915_OVERLAY_ATTRSI915_GEM_EXECBUFFER2I915_GET_SPRITE_COLORKEYI915_SET_SPRITE_COLORKEYI915_GEM_WAITI915_GEM_CONTEXT_CREATEI915_GEM_CONTEXT_DESTROYI915_GEM_SET_CACHINGI915_GEM_GET_CACHINGI915_REG_READI915_GET_RESET_STATSI915_GEM_USERPTRI915_GEM_CONTEXT_GETPARAMI915_GEM_CONTEXT_SETPARAM,, /,C/H/M/VU/V/]/b/؉/.//1/֜//Ϧ/Z/;/,w ,$,(,E/OF/F/G/lG/J/V/Z/[//͗//K/,+,s,7/#/,#,,»,J,½,,/{////A(/>/1V/h/i/j/j/9j/, / /z-,.E, ,,[,,ŋ,,,{,+,,,[,,,[,+,,,,,7,՘,w,7,,ś,,,$,..-),,.-, .-",,.-,.Ħ-<,F.-l,v.2-Ω,֩.f-, .-Ь,ڬ.j-,.ɮ-,.E-,.-4,>.-l,v.=-,ƴ.-,.-,,6.̷-V,^.-,.@-,ƺ.q-/,9.-,.-,.8-,.l-,.-1,9.-f,n.-,.;-,.a-//,W,2,5,p,Cq,qr,\s,t,t,,&,\Q/,,,,,,x,,,f-/E,R/S/S/^/a/b/d/j,2k,r, z,t~,7,E,,ӗ,,,,y,E//'$,aA/F/F/H/I/I/K/u},@~,s, ,,o,,C,,s, /.\/k., ,C , ,7Q ,?R ,2U , ,L , ,f$ ,% ,' ,* ,w1 ,F ,b ,f ,g ,Թ , ,$ ,R /S / (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx (08@HPX`hpx }6},7 }\7}9}<}?}B#}C(}H-}M2}QU7}V<}]A}_F}_aK}jP}]U}ӉZ})_}~d},i}ќn}ۤs}ʦx}U}}6}E}JF}F}G}gG}J}V}W}Z}l[}[}}ȗ}}F}2}}}v}}}}}}!}<(}> },V}xc}h}i}j"}j'}4j,}g1}6};}@2C`FaI}AbN}jbS}oX}q]}|b}g}lorưu} z} }};}}}1}}}f}}WQ}a-}X>}R}S}S}^}`} b}d}@}}\A}F}F}H}I}I }J}N}R }S } $(04<@HLTX`dlpx|  $,08<DHPT\`hltx (,48@DLPX\dhpt| $(04<@HLTX`dlpx|  $,08<DHPT\`hltx (,48A ؘB\\\$oz{1{ր)Ϡ&<f@( a  r?.@N_``ee._5`K`gwx8 8 w   $(,048<@DHLPTX\`dhlptx|license=GPL and additional rightsdescription=Intel Graphicsauthor=Intel Corporationauthor=Tungsten Graphics, Inc.parm=guc_log_level:GuC firmware logging level (-1:disabled (default), 0-3:enabled)parmtype=guc_log_level:intparm=enable_guc_submission:Enable GuC submission (default:false)parmtype=enable_guc_submission:boolparm=edp_vswing:Ignore/Override vswing pre-emph table selection from VBT (0=use value from vbt [default], 1=low power swing(200mV),2=default swing(400mV))parmtype=edp_vswing:intparm=nuclear_pageflip:Force atomic modeset functionality; asynchronous mode is not yet supported. (default: false).parmtype=nuclear_pageflip:boolparm=verbose_state_checks:Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.parmtype=verbose_state_checks:boolparm=mmio_debug:Enable the MMIO debug code for the first N failures (default: off). This may negatively affect performance.parmtype=mmio_debug:intparm=use_mmio_flip:use MMIO flips (-1=never, 0=driver discretion [default], 1=always)parmtype=use_mmio_flip:intparm=enable_cmd_parser:Enable command parsing (1=enabled [default], 0=disabled)parmtype=enable_cmd_parser:intparm=disable_vtd_wa:Disable all VT-d workarounds (default: false)parmtype=disable_vtd_wa:boolparm=disable_display:Disable display (default: false)parmtype=disable_display:boolparm=invert_brightness:Invert backlight brightness (-1 force normal, 0 machine defaults, 1 force inversion), please report PCI device ID, subsystem vendor and subsystem device ID to dri-devel@lists.freedesktop.org, if your machine needs it. It will then be included in an upcoming module version.parmtype=invert_brightness:intparm=load_detect_test:Force-enable the VGA load detect code for testing (default:false). For developers only.parmtype=load_detect_test:boolparm=prefault_disable:Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.parmtype=prefault_disable:boolparm=fastboot:Try to skip unnecessary mode sets at boot time (default: false)parmtype=fastboot:boolparm=enable_ips:Enable IPS (default: true)parmtype=enable_ips:intparm=disable_power_well:Disable display power wells when possible (-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)parmtype=disable_power_well:intparm=preliminary_hw_support:Enable preliminary hardware support.parmtype=preliminary_hw_support:intparm=enable_psr:Enable PSR (default: false)parmtype=enable_psr:intparm=enable_execlists:Override execlists usage. (-1=auto [default], 0=disabled, 1=enabled)parmtype=enable_execlists:intparm=enable_ppgtt:Override PPGTT usage. (-1=auto [default], 0=disabled, 1=aliasing, 2=full)parmtype=enable_ppgtt:intparm=enable_hangcheck:Periodically check GPU activity for detecting hangs. WARNING: Disabling this can cause system wide hangs. (default: true)parmtype=enable_hangcheck:boolparm=reset:Attempt GPU resets (default: true)parmtype=reset:boolparm=vbt_sdvo_panel_type:Override/Ignore selection of SDVO panel mode in the VBT (-2=ignore, -1=auto [default], index in VBT BIOS table)parmtype=vbt_sdvo_panel_type:intparm=lvds_use_ssc:Use Spread Spectrum Clock with panels [LVDS/eDP] (default: auto from VBT)parmtype=lvds_use_ssc:intparm=lvds_channel_mode:Specify LVDS channel mode (0=probe BIOS [default], 1=single-channel, 2=dual-channel)parmtype=lvds_channel_mode:intparm=enable_fbc:Enable frame buffer compression for power savings (default: -1 (use per-chip default))parmtype=enable_fbc:intparm=enable_rc6:Enable power-saving render C-state 6. Different stages can be selected via bitmask values (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. default: -1 (use per-chip default)parmtype=enable_rc6:intparm=semaphores:Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))parmtype=semaphores:intparm=panel_ignore_lid:Override lid status (0=autodetect, 1=autodetect disabled [default], -1=force lid closed, -2=force lid open)parmtype=panel_ignore_lid:intparm=modeset:Use kernel modesetting [KMS] (0=disable, 1=on, -1=force vga console preference [default])parmtype=modeset:intfirmware=i915/bxt_dmc_ver1.binfirmware=i915/skl_dmc_ver1.binfirmware=i915/skl_guc_ver4.binsrcversion=9BEA95468967EE6494009FAalias=pci:v00008086d00005A84sv*sd*bc03sc*i*alias=pci:v00008086d00001A84sv*sd*bc03sc*i*alias=pci:v00008086d00000A84sv*sd*bc03sc*i*alias=pci:v00008086d0000193Asv*sd*bc03sc*i*alias=pci:v00008086d0000193Dsv*sd*bc03sc*i*alias=pci:v00008086d0000193Bsv*sd*bc03sc*i*alias=pci:v00008086d00001932sv*sd*bc03sc*i*alias=pci:v00008086d0000192Asv*sd*bc03sc*i*alias=pci:v00008086d0000192Bsv*sd*bc03sc*i*alias=pci:v00008086d00001926sv*sd*bc03sc*i*alias=pci:v00008086d0000191Dsv*sd*bc03sc*i*alias=pci:v00008086d0000191Asv*sd*bc03sc*i*alias=pci:v00008086d0000191Bsv*sd*bc03sc*i*alias=pci:v00008086d00001912sv*sd*bc03sc*i*alias=pci:v00008086d0000191Esv*sd*bc03sc*i*alias=pci:v00008086d00001921sv*sd*bc03sc*i*alias=pci:v00008086d00001916sv*sd*bc03sc*i*alias=pci:v00008086d0000190Asv*sd*bc03sc*i*alias=pci:v00008086d0000190Bsv*sd*bc03sc*i*alias=pci:v00008086d00001902sv*sd*bc03sc*i*alias=pci:v00008086d0000190Esv*sd*bc03sc*i*alias=pci:v00008086d00001906sv*sd*bc03sc*i*alias=pci:v00008086d000022B3sv*sd*bc03sc*i*alias=pci:v00008086d000022B2sv*sd*bc03sc*i*alias=pci:v00008086d000022B1sv*sd*bc03sc*i*alias=pci:v00008086d000022B0sv*sd*bc03sc*i*alias=pci:v00008086d0000162Dsv*sd*bc03sc*i*alias=pci:v00008086d0000162Asv*sd*bc03sc*i*alias=pci:v00008086d0000162Esv*sd*bc03sc*i*alias=pci:v00008086d0000162Bsv*sd*bc03sc*i*alias=pci:v00008086d00001626sv*sd*bc03sc*i*alias=pci:v00008086d00001622sv*sd*bc03sc*i*alias=pci:v00008086d0000161Dsv*sd*bc03sc*i*alias=pci:v00008086d0000161Asv*sd*bc03sc*i*alias=pci:v00008086d0000160Dsv*sd*bc03sc*i*alias=pci:v00008086d0000160Asv*sd*bc03sc*i*alias=pci:v00008086d0000161Esv*sd*bc03sc*i*alias=pci:v00008086d0000161Bsv*sd*bc03sc*i*alias=pci:v00008086d00001616sv*sd*bc03sc*i*alias=pci:v00008086d00001612sv*sd*bc03sc*i*alias=pci:v00008086d0000160Esv*sd*bc03sc*i*alias=pci:v00008086d0000160Bsv*sd*bc03sc*i*alias=pci:v00008086d00001606sv*sd*bc03sc*i*alias=pci:v00008086d00001602sv*sd*bc03sc*i*alias=pci:v00008086d00000155sv*sd*bc03sc*i*alias=pci:v00008086d00000157sv*sd*bc03sc*i*alias=pci:v00008086d00000F33sv*sd*bc03sc*i*alias=pci:v00008086d00000F32sv*sd*bc03sc*i*alias=pci:v00008086d00000F31sv*sd*bc03sc*i*alias=pci:v00008086d00000F30sv*sd*bc03sc*i*alias=pci:v00008086d00000D26sv*sd*bc03sc*i*alias=pci:v00008086d00000D16sv*sd*bc03sc*i*alias=pci:v00008086d00000D06sv*sd*bc03sc*i*alias=pci:v00008086d00000A2Esv*sd*bc03sc*i*alias=pci:v00008086d00000A1Esv*sd*bc03sc*i*alias=pci:v00008086d00000A0Esv*sd*bc03sc*i*alias=pci:v00008086d00000A26sv*sd*bc03sc*i*alias=pci:v00008086d00000A16sv*sd*bc03sc*i*alias=pci:v00008086d00000A06sv*sd*bc03sc*i*alias=pci:v00008086d00000C26sv*sd*bc03sc*i*alias=pci:v00008086d00000C16sv*sd*bc03sc*i*alias=pci:v00008086d00000C06sv*sd*bc03sc*i*alias=pci:v00008086d00000426sv*sd*bc03sc*i*alias=pci:v00008086d00000416sv*sd*bc03sc*i*alias=pci:v00008086d00000406sv*sd*bc03sc*i*alias=pci:v00008086d00000D2Esv*sd*bc03sc*i*alias=pci:v00008086d00000D1Esv*sd*bc03sc*i*alias=pci:v00008086d00000D0Esv*sd*bc03sc*i*alias=pci:v00008086d00000D2Bsv*sd*bc03sc*i*alias=pci:v00008086d00000D1Bsv*sd*bc03sc*i*alias=pci:v00008086d00000D0Bsv*sd*bc03sc*i*alias=pci:v00008086d00000D2Asv*sd*bc03sc*i*alias=pci:v00008086d00000D1Asv*sd*bc03sc*i*alias=pci:v00008086d00000D0Asv*sd*bc03sc*i*alias=pci:v00008086d00000D22sv*sd*bc03sc*i*alias=pci:v00008086d00000D12sv*sd*bc03sc*i*alias=pci:v00008086d00000D02sv*sd*bc03sc*i*alias=pci:v00008086d00000A2Bsv*sd*bc03sc*i*alias=pci:v00008086d00000A1Bsv*sd*bc03sc*i*alias=pci:v00008086d00000A0Bsv*sd*bc03sc*i*alias=pci:v00008086d00000A2Asv*sd*bc03sc*i*alias=pci:v00008086d00000A1Asv*sd*bc03sc*i*alias=pci:v00008086d00000A0Asv*sd*bc03sc*i*alias=pci:v00008086d00000A22sv*sd*bc03sc*i*alias=pci:v00008086d00000A12sv*sd*bc03sc*i*alias=pci:v00008086d00000A02sv*sd*bc03sc*i*alias=pci:v00008086d00000C2Esv*sd*bc03sc*i*alias=pci:v00008086d00000C1Esv*sd*bc03sc*i*alias=pci:v00008086d00000C0Esv*sd*bc03sc*i*alias=pci:v00008086d00000C2Bsv*sd*bc03sc*i*alias=pci:v00008086d00000C1Bsv*sd*bc03sc*i*alias=pci:v00008086d00000C0Bsv*sd*bc03sc*i*alias=pci:v00008086d00000C2Asv*sd*bc03sc*i*alias=pci:v00008086d00000C1Asv*sd*bc03sc*i*alias=pci:v00008086d00000C0Asv*sd*bc03sc*i*alias=pci:v00008086d00000C22sv*sd*bc03sc*i*alias=pci:v00008086d00000C12sv*sd*bc03sc*i*alias=pci:v00008086d00000C02sv*sd*bc03sc*i*alias=pci:v00008086d0000042Esv*sd*bc03sc*i*alias=pci:v00008086d0000041Esv*sd*bc03sc*i*alias=pci:v00008086d0000040Esv*sd*bc03sc*i*alias=pci:v00008086d0000042Bsv*sd*bc03sc*i*alias=pci:v00008086d0000041Bsv*sd*bc03sc*i*alias=pci:v00008086d0000040Bsv*sd*bc03sc*i*alias=pci:v00008086d0000042Asv*sd*bc03sc*i*alias=pci:v00008086d0000041Asv*sd*bc03sc*i*alias=pci:v00008086d0000040Asv*sd*bc03sc*i*alias=pci:v00008086d00000422sv*sd*bc03sc*i*alias=pci:v00008086d00000412sv*sd*bc03sc*i*alias=pci:v00008086d00000402sv*sd*bc03sc*i*alias=pci:v00008086d0000016Asv*sd*bc03sc*i*alias=pci:v00008086d0000015Asv*sd*bc03sc*i*alias=pci:v00008086d00000162sv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t_fmt_i915_gem_object_pwriteprint_fmt_i915_gem_object_change_domainprint_fmt_i915_page_table_entry_updateprint_fmt_i915_page_directory_pointer_entry_allocprint_fmt_i915_page_directory_entry_allocprint_fmt_i915_px_entryprint_fmt_i915_vaprint_fmt_i915_vma_unbindprint_fmt_i915_vma_bindprint_fmt_i915_gem_shrinkprint_fmt_i915_gem_object_createprint_fmt_i915_pipe_update_endprint_fmt_i915_pipe_update_vblank_evadedprint_fmt_i915_pipe_update_startintel_lrc.cgen8_get_seqnogen8_set_seqnogen8_emit_flush_coherentl3_wai915_page_dir_dma_addrintel_lr_context_do_pingen8_logical_ring_put_irqgen8_logical_ring_get_irqexeclists_check_remove_requestbxt_a_set_seqnobxt_a_get_seqnogen8_emit_flushlrc_destroy_wa_ctx_obj__func__.53311__func__.53582logical_ring_init__key.52847gen8_emit_bb_startgen8_emit_flush_rendergen8_init_rcs_context__warned.51431__func__.51158gen8_init_common_ring__func__.52418gen8_init_render_ringgen9_init_render_ringexeclists_update_contextexeclists_context_unqueuegen8_emit_request__func__.52327__func__.52285intel_mocs.cemit_mocs_control_table__func__.50393skylake_mocs_table__func__.50436broxton_mocs_table__warned.50323intel_ringbuffer.c__intel_ring_advancering_write_tailgen6_ring_get_seqnoring_get_seqnoring_set_seqnopc_render_get_seqnopc_render_set_seqnostop_ringgen6_bsd_ring_write_tailwa_addgen8_init_workaroundsgen9_init_workaroundshsw_vebox_put_irqgen8_ring_put_irqgen8_ring_get_irqi9xx_ring_put_irqi9xx_ring_get_irqi8xx_ring_put_irqi8xx_ring_get_irqhsw_vebox_get_irqgen6_ring_put_irqgen5_ring_put_irqgen6_ring_get_irqgen5_ring_get_irqinit_ring_common__func__.50869CSWTCH.1163init_render_ringrender_ring_cleanup__func__.51034intel_init_ring_buffer__key.53805__func__.53633gen6_ring_flushgen6_add_requestgen8_ring_dispatch_execbuffergen8_ring_syncgen8_xcs_signalgen6_ring_dispatch_execbuffergen6_ring_syncgen6_signalgen6_bsd_ring_flushbsd_ring_flushi9xx_add_requesti965_dispatch_execbuffergen8_rcs_signalintel_rcs_ctx_init__func__.51080hsw_ring_dispatch_execbuffergen2_render_ring_flushgen4_render_ring_flushi915_dispatch_execbuffergen8_emit_pipe_controlgen8_render_ring_flushpc_render_add_requestgen7_render_ring_flushgen6_render_ring_flushi830_dispatch_execbufferintel_uncore.cfw_domains_put__intel_uncore_forcewake_getironlake_do_reseti915_do_resetg4x_reset_completeg33_do_resetg4x_do_resetassert_device_not_suspended__warned.50464gen2_read64gen2_read32gen2_read16gen2_read8gen2_write64gen2_write32gen2_write16gen2_write8gen5_read64gen5_read32gen5_read16gen5_read8gen5_write64gen5_write32gen5_write16gen5_write8gen6_gt_check_fifodbgfw_domains_put_with_fifo__gen6_gt_wait_for_fifohsw_unclaimed_reg_debugforcewake_domain_namesfw_domains_getfw_domains_get_with_thread_statusfw_domain_initintel_uncore_fw_release_timervgpu_read64vgpu_read32vgpu_read16vgpu_read8vgpu_write64vgpu_write32vgpu_write16vgpu_write8gen6_write64gen6_write32gen6_write16gen6_write8__force_wake_get__intel_uncore_forcewake_putgen8_do_resetgen6_do_resethsw_unclaimed_reg_detectmmio_debug_once.51373__func__.51374hsw_write64hsw_write32hsw_write16hsw_write8__intel_uncore_early_sanitizegen9_write8gen9_write16gen9_write32gen9_write64gen9_read8gen9_read16gen9_read32gen9_read64chv_write8chv_write16chv_write32chv_write64chv_read8chv_read16chv_read32chv_read64vlv_read8vlv_read16vlv_read32vlv_read64gen8_write8gen8_write16gen8_write32gen8_write64gen6_read8gen6_read16gen6_read32gen6_read64gen8_shadowed_regsgen9_shadowed_regsintel_guc_loader.cCSWTCH.892direct_interrupts_to_host__func__.50784__func__.50857guc_ucode_xfer_dma__func__.50519__func__.50583__func__.50712__mod_firmware63i915_guc_submission.chost2guc_actionguc_fini_ctx_descgem_allocate_guc_objguc_init_ctx_descgem_release_guc_objguc_client_free__func__.51047__func__.50670__func__.50649intel_renderstate_gen6.cgen6_null_state_relocsgen6_null_state_batchintel_renderstate_gen7.cgen7_null_state_relocsgen7_null_state_batchintel_renderstate_gen8.cgen8_null_state_relocsgen8_null_state_batchintel_renderstate_gen9.cgen9_null_state_relocsgen9_null_state_batchintel_audio.cilk_audio_codec_enableilk_audio_codec_disablehsw_audio_codec_enablehsw_audio_codec_disableg4x_audio_codec_enableg4x_audio_codec_disablei915_audio_component_bind_opsi915_audio_component_unbindi915_audio_component_bindi915_audio_component_opsaudio_config_hdmi_pixel_clockhdmi_audio_clock__func__.50588__func__.50694__func__.50728i915_audio_component_sync_audio_rateaud_ncts__func__.51342__func__.50790__func__.50919__func__.51005i915_audio_component_get_poweri915_audio_component_get_cdclk_freq__warned.51277i915_audio_component_put_poweri915_audio_component_codec_wake_override__func__.50836__func__.51103intel_atomic.c__func__.50565intel_atomic_plane.cintel_plane_atomic_update__func__.50673__func__.50658intel_plane_atomic_check__func__.50563intel_bios.cfind_sectionintel_no_opregion_vbt_callback__func__.51658validate_vbt__func__.51677fill_detail_timing_dataintel_no_opregion_vbtpanel_type__func__.51534__func__.50812__func__.50595__func__.50973__func__.50710__func__.50657__func__.51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did__func__.51351intel_crt_ddc_get_modesintel_crt_get_modesintel_crt_detect_ddc__func__.51387intel_crt_destroyintel_crt_detect__func__.51565__func__.51254__func__.51163__func__.51077__func__.51444intel_no_crt_dmi_callbackintel_no_crtintel_crt_connector_funcsintel_crt_enc_funcshsw_crt_get_configintel_crt_connector_helper_funcsintel_crt_get_configintel_crt_get_hw_stateintel_ddi.chsw_ddi_wrpll_disablehsw_ddi_spll_disableskl_ddi_pll_disableskl_dpll_regsbroxton_phy_uninitbxt_ddi_pll_disableintel_ddi_destroyintel_ddi_funcsintel_ddi_compute_configintel_enable_ddiintel_ddi_pre_enableintel_disable_ddiintel_ddi_post_disable__func__.54228hsw_ddi_spll_enablehsw_ddi_wrpll_enableintel_wait_ddi_buf_idlebxt_ddi_vswing_sequencebxt_ddi_translations_hdmibxt_ddi_translations_edpbxt_ddi_translations_dp__func__.52504skl_y_ddi_translations_hdmiskl_ddi_translations_hdmiskl_y_ddi_translations_dpskl_u_ddi_translations_dpskl_ddi_translations_dpskl_ddi_translations_edpskl_y_ddi_translations_edpskl_u_ddi_translations_edp__func__.52645intel_ddi_get_crtc_encoderhsw_ddi_calc_wrpll_link__func__.50899ddi_get_encoder_portskl_ddi_pll_get_hw_statebxt_ddi_pll_get_hw_state__func__.53751hsw_ddi_spll_get_hw_statehsw_ddi_wrpll_get_hw_statebxt_ddi_pll_enableskl_ddi_pll_enablebroxton_phy_initskl_ddi_pll_namesbxt_ddi_pll_names__func__.52334ddi_dotclock_get__func__.54105hsw_ddi_translations_dphsw_ddi_translations_fdihsw_ddi_translations_hdmibdw_ddi_translations_dpbdw_ddi_translations_fdibdw_ddi_translations_hdmibdw_ddi_translations_edpdividers.51750__func__.51778__func__.51535bxt_dp_clk_val__func__.51902even_dividers.51745odd_dividers.51746intel_dp_mst.cintel_dp_mst_enc_get_hw_stateintel_dp_mst_set_propertyintel_dp_mst_mode_validintel_mst_atomic_best_encoderintel_mst_best_encoderintel_dp_mst_get_hw_stateintel_dp_mst_hotplugintel_dp_mst_connector_destroyintel_dp_destroy_mst_connectorintel_dp_register_mst_connectorintel_dp_add_mst_connectorintel_dp_mst_connector_funcsintel_dp_mst_connector_helper_funcsintel_dp_mst_get_modesintel_dp_mst_detectintel_dp_mst_encoder_destroymst_cbsintel_dp_mst_enc_funcsintel_dp_mst_compute_configintel_mst_disable_dpintel_mst_post_disable_dpintel_mst_pre_enable_dpintel_mst_enable_dpintel_dp_mst_enc_get_config__func__.50853__func__.50802__func__.50759__func__.50737intel_dp.cvlv_pipe_has_pp_onvlv_pipe_has_vdd_onvlv_pipe_anyvlv_initial_pps_pipevlv_get_aux_clock_dividerskl_get_aux_clock_divideri9xx_get_aux_send_ctlskl_get_aux_send_ctlintel_dp_source_ratesskl_ratesdefault_ratesbxt_ratesintel_dp_prepareport_mapping.57086intel_dp_dpcd_read_wakeintel_dp_probe_oui__func__.55898intel_dp_probe_mst__func__.55928__func__.53605pps_lockintel_dp_link_down__func__.55675vlv_post_disable_dpintel_dp_sink_ratesintel_dp_common_ratesintel_dp_mode_validilk_get_aux_clock_dividerhsw_get_aux_clock_dividerCSWTCH.1597intel_dp_init_panel_power_sequencer_registersvlv_power_sequencer_pipe__func__.57459vlv_steal_power_sequencerintel_dp_init_panel_power_sequencervlv_dpllchv_dpll__func__.50920__func__.51076_pp_ctrl_regedp_have_panel_vddironlake_get_pp_control__func__.57176_pp_stat_regedp_panel_vdd_off_sync__func__.53204vlv_detach_power_sequencer__func__.54364__func__.54395edp_have_panel_powervlv_initial_power_sequencer_setupi9xx_get_aux_clock_divideredp_panel_vdd_schedule_offintel_edp_panel_vdd_sanitize__func__.56938pps_unlockintel_dp_encoder_resetedp_notify_handleredp_panel_vdd_workilk_post_disable_dpg4x_pre_enable_dp__func__.52769__func__.53536_intel_dp_set_link_train__func__.57809_intel_edp_backlight_offwait_panel_status__func__.52963__func__.53394__func__.53033edp_panel_vdd_offvlv_dp_pre_pll_enablechv_data_lane_soft_resetchv_post_disable_dpchv_dp_post_pll_disablechv_dp_pre_pll_enableintel_dp_encoder_suspendintel_dp_get_config__func__.53772intel_dp_get_hw_state__func__.53649intel_dp_get_modesintel_dp_set_edidintel_dp_force__func__.56756intel_dp_connector_destroyintel_dp_set_property__func__.56835intel_dp_set_link_trainintel_dp_set_drrs_state__func__.57657intel_edp_drrs_downclock_workintel_dp_connector_unregister__func__.56436__func__.56485__func__.56411__func__.56459__func__.56513intel_dp_sink_crc_stop__func__.55968__func__.56042intel_dp_set_signal_levelsCSWTCH.1595__func__.55232__func__.55197__func__.55176intel_dp_update_link_trainCSWTCH.1585CSWTCH.1587CSWTCH.1589CSWTCH.1593CSWTCH.1591__func__.53488gen4_dpllpch_dpll__func__.52534intel_dp_reset_link_train.clone.0intel_dp_link_training_clock_recovery__func__.55504__func__.55601intel_dp_check_mst_status__func__.56205snprintf_int_array.clone.1intel_dp_print_rates__func__.52426intel_dp_get_dpcd__func__.55789intel_dp_detect_dpcdintel_dp_detect__func__.56679__func__.56157__func__.56115intel_dp_connector_funcsintel_dp_connector_helper_funcsCSWTCH.1614intel_dp_aux_transfer__func__.58158__key.57964__func__.57967intel_edp_backlight_power__func__.58029__func__.51958intel_dp_enc_funcsintel_disable_dpvlv_pre_enable_dpvlv_enable_dpg4x_enable_dpchv_pre_enable_dpintel_dp_check_link_status__func__.56265__func__.56990_intel_edp_backlight_on__func__.53506__func__.53454wait_panel_power_cycle__func__.53043edp_panel_vdd_on__func__.53111intel_dp_aux_chlast_status.51737__func__.51448__func__.51756edp_panel_on__func__.53023__func__.53307intel_enable_dp__func__.54260__func__.54445intel_dsi.cintel_dsi_host_attachintel_dsi_host_detachtxbyteclkhsintel_dsi_detectintel_dsi_mode_valid__func__.52581intel_dsi_enable_nop__func__.52038intel_dsi_get_modes__func__.53285intel_dsi_connector_destroy__func__.53310intel_dsi_encoder_destroyintel_dsi_funcsintel_dsi_compute_configintel_dsi_pre_pll_enableintel_dsi_pre_enableintel_dsi_pre_disableintel_dsi_post_disableintel_dsi_get_hw_stateintel_dsi_get_configintel_dsi_host_opsintel_dsi_connector_funcsintel_dsi_connector_helper_funcs__func__.53342intel_dsi_host_transferwait_for_dsi_fifo_empty__func__.52520__func__.52082__func__.52176__func__.53266__func__.51523dpi_send_cmd.clone.0__func__.51910__func__.51971__func__.51643intel_dsi_panel_vbt.cgeneric_exec_sequenceexec_elem__func__.51051seq_namevbt_panel_enablevbt_panel_preparevbt_panel_unpreparevbt_panel_disableCSWTCH.883CSWTCH.885vbt_panel_funcs__func__.51166vbt_panel_get_modesmipi_exec_gpiogtablemipi_exec_delaymipi_exec_send_packet__func__.50954intel_dsi_pll.c__func__.50745__func__.50761lfsr_converts__func__.50688__func__.51065__func__.50647intel_dvo.cintel_dvo_connector_get_hw_stateintel_dvo_get_hw_stateintel_dvo_get_configintel_disable_dvointel_enable_dvointel_dvo_mode_validintel_dvo_pre_enableintel_dvo_get_modesintel_dvo_destroyintel_dvo_detect__func__.50720intel_dvo_enc_destroyintel_dvo_enc_funcsintel_dvo_compute_configintel_dvo_devicesintel_dvo_connector_funcsintel_dvo_connector_helper_funcsintel_hdmi.cg4x_infoframe_enabledibx_infoframe_enabledcpt_infoframe_enabledvlv_infoframe_enabledhsw_infoframe_enabledintel_hdmi_preparevlv_enable_hdmiintel_disable_hdmipch_post_disable_hdmihdmi_port_clock_validintel_hdmi_mode_validintel_hdmi_pre_enableassert_hdmi_port_disabledintel_hdmi_set_gcp_infoframeg4x_infoframe_index__func__.50695g4x_infoframe_enablecpt_write_infoframeibx_write_infoframeg4x_write_infoframevlv_write_infoframehsw_dip_data_reg__func__.50743hsw_infoframe_enable__func__.50725hsw_write_infoframeintel_enable_hdmi_audiog4x_enable_hdmiibx_enable_hdmicpt_enable_hdmivlv_hdmi_post_disablevlv_hdmi_pre_pll_enablechv_hdmi_post_disablevlv_hdmi_pre_enablechv_hdmi_post_pll_disablechv_hdmi_pre_enablechv_hdmi_pre_pll_enableintel_hdmi_get_configintel_hdmi_get_hw_stateg4x_disable_hdmipch_disable_hdmiintel_hdmi_get_modesintel_hdmi_set_edidintel_hdmi_force__func__.52363intel_hdmi_destroyintel_hdmi_set_propertyintel_hdmi_detect__func__.52325intel_hdmi_connector_funcsintel_hdmi_connector_helper_funcs__func__.52906vlv_set_infoframesg4x_set_infoframeshsw_set_infoframescpt_set_infoframesibx_set_infoframesintel_hdmi_enc_funcsintel_write_infoframeintel_hdmi_set_avi_infoframeintel_hdmi_set_spd_infoframeintel_hdmi_set_hdmi_infoframe__func__.51178__func__.52190intel_i2c.cgmbus_pins_sklgmbus_pins_bxtgmbus_pins_bdwgmbus_pinsintel_i2c_quirk_setget_reservedget_clockget_dataset_clockset_dataintel_gpio_post_xfergmbus_func__func__.51177gmbus_wait_hw_statusgmbus_xfer_readgmbus_wait_idlegmbus_xfer__func__.50966__key.51066__key.51067gmbus_algorithmintel_gpio_pre_xferintel_lvds.cintel_lvds_mode_validintel_lvds_get_modesintel_lvds_destroyintel_lvds_set_property__func__.51620intel_lvds_detect__func__.51518intel_no_lvds_dmi_callbackintel_dual_link_lvds_callbackintel_no_modeset_on_lid_dmi_callbackintel_no_lvdsintel_lvds_connector_funcsintel_lvds_enc_funcsintel_enable_lvdsintel_pre_enable_lvdsintel_lvds_compute_configgmch_disable_lvdsintel_lvds_get_hw_stateintel_lvds_get_configintel_lvds_connector_helper_funcsintel_lid_notify__func__.51837pch_disable_lvdspch_post_disable_lvdsintel_dual_link_lvdsintel_no_modeset_on_lidintel_disable_lvds__func__.51460intel_panel.ccentre_horizontallycentre_verticallylpt_get_backlightpch_get_backlightbxt_get_backlightlpt_set_backlightpch_set_backlightbxt_set_backlightspt_hz_to_pwmlpt_hz_to_pwmi965_hz_to_pwmvlv_setup_backlightvlv_enable_backlightvlv_disable_backlightvlv_set_backlightvlv_get_backlightvlv_hz_to_pwmlpt_setup_backlightlpt_enable_backlightlpt_disable_backlighti9xx_setup_backlighti9xx_enable_backlighti9xx_disable_backlighti9xx_set_backlighti9xx_get_backlighti9xx_hz_to_pwmbxt_setup_backlightbxt_enable_backlightbxt_disable_backlightpch_setup_backlightpch_enable_backlightpch_disable_backlightpch_hz_to_pwmi965_setup_backlighti965_enable_backlighti965_disable_backlightscaleintel_panel_compute_brightness_vlv_get_backlightintel_panel_actually_set_backlight__func__.51046__func__.51334get_backlight_max_vbt__func__.51814get_backlight_min_vbt__func__.51852__func__.51397__func__.51439__func__.51124__func__.51250__func__.51483intel_backlight_device_update_status__func__.51573intel_panel_get_backlight__func__.50912intel_backlight_device_ops__func__.51629intel_backlight_device_get_brightness__func__.52184__func__.51531__func__.51222__func__.51294intel_sdvo.cintel_sdvo_write_sdvoxpch_disable_sdvointel_sdvo_mode_validintel_sdvo_ddc_proxy_funcintel_sdvo_enc_destroyintel_sdvo_debug_writesdvo_cmd_names__func__.51122intel_sdvo_write_cmdintel_sdvo_ddc_proxy_xferintel_sdvo_enable_hotplugintel_sdvo_read_byte__func__.51069intel_sdvo_read_responsecmd_status_names__func__.51256intel_sdvo_get_valueintel_sdvo_connector_get_hw_stateintel_sdvo_get_hw_stateintel_sdvo_set_valueintel_disable_sdvopch_post_disable_sdvointel_sdvo_set_timingintel_sdvo_connector_allocintel_sdvo_connector_initintel_sdvo_connector_funcsintel_sdvo_connector_helper_funcsintel_sdvo_connector_unregisterintel_sdvo_analog_init__func__.53420intel_sdvo_destroyintel_sdvo_get_analog_edidintel_sdvo_get_modessdvo_tv_modes__func__.52828__func__.52741__func__.52656intel_sdvo_set_propertyintel_sdvo_detect__func__.52679intel_sdvo_dvi_init__func__.53341intel_sdvo_create_enhance_property__func__.53660__func__.53971__func__.54016intel_sdvo_tv_inittv_format_names__func__.53385intel_sdvo_lvds_init__func__.53450intel_sdvo_ddc_proxyintel_sdvo_enc_funcsintel_sdvo_compute_configintel_sdvo_pre_enableintel_enable_sdvointel_sdvo_get_config__func__.54087__func__.53481__func__.52487CSWTCH.1028__func__.52263__func__.52421intel_sdvo_get_dtd_from_modeintel_sdvo_set_output_timings_from_modeintel_sdvo_get_mode_from_dtdintel_sdvo_get_preferred_input_mode__func__.51906intel_sdvo_set_avi_infoframe__func__.51752intel_tv.cintel_tv_get_hw_stateintel_disable_tvintel_tv_get_configintel_tv_mode_findtv_modesintel_tv_mode_validintel_tv_compute_config__func__.50885intel_tv_get_modesinput_res_tableintel_tv_destroyintel_tv_set_propertyintel_tv_detectreported_modes__func__.51201__func__.51298intel_enable_tv__func__.51549intel_tv_connector_funcsintel_tv_enc_funcsintel_tv_pre_enableintel_tv_connector_helper_funcshdtv_csc_yprpbsdtv_csc_yprpbcomponent_levelsntsc_m_levels_compositentsc_m_levels_svideontsc_m_csc_compositentsc_m_csc_svideofilter_tablentsc_j_levels_compositentsc_j_levels_svideontsc_j_csc_compositentsc_j_csc_svideopal_m_levels_compositepal_m_levels_svideopal_m_csc_compositepal_m_csc_svideopal_n_levels_compositepal_n_levels_svideopal_n_csc_compositepal_n_csc_svideopal_levels_compositepal_levels_svideopal_csc_compositepal_csc_svideoi915_vgpu.cvgt_balloon_spacebl_info__func__.50391i915_dma.ci915_gem_reject_pin_ioctli915_getparam__func__.51543intel_teardown_mchbarbroadwell_sseu_info_init__key.52739__key.52743__key.52744__key.52745__key.52746i915_vga_set_decodei915_switcheroo_ops__func__.52037__func__.52481__func__.51716i915_switcheroo_can_switchi915_switcheroo_set_statei915.mod.c_rheldata__mod_srcversion785__mod_alias783__mod_alias782__mod_alias781__mod_alias780__mod_alias779__mod_alias778__mod_alias777__mod_alias776__mod_alias775__mod_alias774__mod_alias773__mod_alias772__mod_alias771__mod_alias770__mod_alias769__mod_alias768__mod_alias767__mod_alias766__mod_alias765__mod_alias764__mod_alias763__mod_alias762__mod_alias761__mod_alias760__mod_alias759__mod_alias758__mod_alias757__mod_alias756__mod_alias755__mod_alias754__mod_alias753__mod_alias752__mod_alias751__mod_alias750__mod_alias749__mod_alias748__mod_alias747__mod_alias746__mod_alias745__mod_alias744__mod_alias743__mod_alias742__mod_alias741__mod_alias740__mod_alias739__mod_alias738__mod_alias737__mod_alias736__mod_alias735__mod_alias734__mod_alias733__mod_alias732__mod_alias731__mod_alias730__mod_alias729__mod_alias728__mod_alias727__mod_alias726__mod_alias725__mod_alias724__mod_alias723__mod_alias722__mod_alias721__mod_alias720__mod_alias719__mod_alias718__mod_alias717__mod_alias716__mod_alias715__mod_alias714__mod_alias713__mod_alias712__mod_alias711__mod_alias710__mod_alias709__mod_alias708__mod_alias707__mod_alias706__mod_alias705__mod_alias704__mod_alias703__mod_alias702__mod_alias701__mod_alias700__mod_alias699__mod_alias698__mod_alias697__mod_alias696__mod_alias695__mod_alias694__mod_alias693__mod_alias692__mod_alias691__mod_alias690__mod_alias689__mod_alias688__mod_alias687__mod_alias686__mod_alias685__mod_alias684__mod_alias683__mod_alias682__mod_alias681__mod_alias680__mod_alias679__mod_alias678__mod_alias677__mod_alias676__mod_alias675__mod_alias674__mod_alias673__mod_alias672__mod_alias671__mod_alias670__mod_alias669__mod_alias668__mod_alias667__mod_alias666__mod_alias665__mod_alias664__mod_alias663__mod_alias662__mod_alias661__mod_alias660__mod_alias659__mod_alias658__mod_alias657__mod_alias656__mod_alias655__mod_alias654__mod_alias653__mod_alias652__mod_alias651__mod_alias650__mod_alias649__mod_alias648__mod_alias647__mod_alias646__mod_alias645__mod_alias644__mod_alias643__mod_alias642__mod_alias641__mod_alias640__mod_alias639__mod_alias638__mod_alias637__mod_alias636__mod_alias635__mod_alias634__mod_alias633__mod_alias632__mod_alias631__mod_alias630__mod_alias629__module_depends____versions__mod_vermagic5register_shrinker2intel_ddi_pll_selectintel_guc_resumens_to_timevali915_gem_object_set_to_cpu_domaindrm_framebuffer_cleanupdrm_atomic_helper_plane_destroy_statei915_gem_faultdrm_atomic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